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S3CK225/fk225 calmrisc 8-bit cmos microcontroller user's manual revision 1
important notice the information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. this publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of samsung or others. samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by the customer's technical experts. samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the samsung product could create a situation where personal injury or death may occur. should the buyer purchase or use a samsung product for any such unintended or unauthorized application, the buyer shall indemnify and hold samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that samsung was negligent regarding the design or manufacture of said product. S3CK225/fk225 8-bit cmos microcontroller user's manual, revision 1 publication number: 21-s3-ck225/fk225-032003 ? 2003 samsung electronics all rights reserved. no part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of samsung electronics. samsung electronics' microcontroller business has been awarded full iso-14001 certification (bvq1 certificate no. 9330). all semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. samsung electronics co., ltd. san #24 nongseo-ri, giheung- eup yongin-city, gyeonggi-do, korea c.p.o. box #37, suwon 449-900 tel: (82)-(331)-209-1907 fax: (82)-(331)-209-1889 home-page url: http://www.samsungsemi.com/ printed in the republic of korea
S3CK225/fk225 microcontroller iii preface the S3CK225/fk225 microcontroller user's manual is designed for application designers and programmers who are using the S3CK225/fk225 microcontroller for application development. it is organized in two main parts: part i programming model part ii hardware descriptions part i contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. it has nine chapters: chapter 1 product overview chapter 2 address spaces chapter 3 register chapter 4 memory map chapter 5 hardware stack chapter 6 exceptions chapter 7 instruction set chapter 1, "product overview," is a high-level introduction to S3CK225/fk225 with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types. chapter 2, "address spaces," describes program and data memory spaces. chapter 2 also describes rom code option. chapter 3, "register," describes the special registers. chapter 4, "memory map," describes the internal register file. chapter 5, "hardware stack," describes the S3CK225/fk225 hardware stack structure in detail. chapter 6, "exception," describes the S3CK225/fk225 exception structure in detail. a basic familiarity with the information in part i will help you to understand the hardware module descriptions in part ii. if you are not yet familiar with the s3ck-series microcontroller family and are reading this manual for the first time, we recommend that you first read chapters 1?3 carefully. then, briefly look over the detailed information in chapters 4, 5, 6 and 7. later, you can reference the information in part i as necessary. part ii "hardware descriptions," has detailed information about specific hardware components of the S3CK225/fk225 microcontroller. also included in part ii are electrical, mechanical. it has 20 chapters: chapter 8 clock circuit chapter 9 reset and power-down chapter 10 i/o ports chapter 11 basic timer/watchdog timer chapter 12 watch timer chapter 13 16-bit timer 0 chapter 14 16-bit timer 1 chapter 15 8-bit timer 2 chapter 16 8-bit timer 3 chapter 17 serial i/o interface chapter 18 lcd controller/driver chapter 19 10-bt a/d converter chapter 20 d/a converter chapter 21 operational amplifier chapter 22 electrical data chapter 23 mechanical data chapter 24 s3fk225 flash mcu chapter 25 development tools one order form is included at the back of this manual to facilitate customer order for S3CK225/fk225 microcontrollers: the flash factory writing order form. you can photocopy this form, fill it out, and then forward it to your local samsung sales representative.

S3CK225/fk225 microcontroller v table of contents part i ? programming model chapter 1 product overview overview ................................ ................................ ................................ ................................ ................. 1-1 features ................................ ................................ ................................ ................................ .................. 1-5 block diagram ................................ ................................ ................................ ................................ ......... 1-7 pin assignment ................................ ................................ ................................ ................................ ........ 1-8 pin descriptions ................................ ................................ ................................ ................................ ....... 1-9 pin circuits ................................ ................................ ................................ ................................ .............. 1-11 chapter 2 address spaces overview ................................ ................................ ................................ ................................ ................. 2-1 program memory (rom) ................................ ................................ ................................ ......................... 2-1 rom code option (rcod_opt) ................................ ................................ ................................ ............ 2-4 data memory organization ................................ ................................ ................................ ...................... 2-6 chapter 3 register overview ................................ ................................ ................................ ................................ ................. 3-1 index registers: idh, idl0 and idl1 ................................ ................................ ............................... 3-2 link registers: ilx, ilh and ill ................................ ................................ ................................ ..... 3-2 status register 0: sr0 ................................ ................................ ................................ .................... 3-3 status register 1: sr1 ................................ ................................ ................................ .................... 3-4 chapter 4 memory map overview ................................ ................................ ................................ ................................ ................. 4-1
vi S3CK225/fk225 micr ocontroller table of contents (continued) chapter 5 hardware stack overview ................................ ................................ ................................ ................................ ................. 5-1 chapter 6 exceptions overview ................................ ................................ ................................ ................................ ................. 6-1 hardware reset ................................ ................................ ................................ ............................... 6-1 irq[0] exception ................................ ................................ ................................ ............................. 6-2 irq[1] exception (level-sensitive) ................................ ................................ ................................ .. 6-2 hardware stack full exception ................................ ................................ ................................ ........ 6-2 break exception ................................ ................................ ................................ .............................. 6-2 exceptions (or interrupts) ................................ ................................ ................................ ................ 6-3 interrupt mask registers ................................ ................................ ................................ .................. 6-5 interrupt priority register ................................ ................................ ................................ ................. 6-6 chapter 7 instruction set overview ................................ ................................ ................................ ................................ ................. 7-1 glossary ................................ ................................ ................................ ................................ .......... 7-1 instruction set map ................................ ................................ ................................ ................................ .. 7-2 quick reference ................................ ................................ ................................ ................................ ...... 7-9 instruction group summary ................................ ................................ ................................ ..................... 7-12 alu instructions ................................ ................................ ................................ .............................. 7-12 shift/rotate instructions ................................ ................................ ................................ ................... 7-16 load instructions ................................ ................................ ................................ ............................. 7-18 branch instructions ................................ ................................ ................................ .......................... 7-21 bit manipulation instructions ................................ ................................ ................................ ............ 7-25 miscellaneous instruction ................................ ................................ ................................ ................. 7- 26 pseudo instructions ................................ ................................ ................................ ...................... 7-29
S3CK225/fk225 microcontroller vii table of contents (continued) part ii ? hardware descriptions chapter 8 clock circuit system clock circuit ................................ ................................ ................................ ............................... 8-1 chapter 9 reset and power-down overview ................................ ................................ ................................ ................................ ................. 9-1 chapter 10 i/o ports port 0 ................................ ................................ ................................ ................................ ....................... 10-1 port 1 ................................ ................................ ................................ ................................ ....................... 10-2 port 2 ................................ ................................ ................................ ................................ ....................... 10-3 port 3 ................................ ................................ ................................ ................................ ....................... 10-4 port 4 ................................ ................................ ................................ ................................ ....................... 10-5 port 5 ................................ ................................ ................................ ................................ ....................... 10-6 port 6 ................................ ................................ ................................ ................................ ....................... 10-7 port 7 ................................ ................................ ................................ ................................ ....................... 10-7 chapter 11 basic timer/watchdog timer overview ................................ ................................ ................................ ................................ ................. 11-1 block diagram ................................ ................................ ................................ ................................ . 11-2 chapter 12 watch timer overview ................................ ................................ ................................ ................................ ................. 12-1 watch timer circuit diagram ................................ ................................ ................................ .......... 12-2 chapter 13 16-bit timer 0 overview ................................ ................................ ................................ ................................ ......... 13-1 function description ................................ ................................ ................................ ........................ 13-2 timer 0 control register (t0con) ................................ ................................ ................................ .. 13-3 block diagram ................................ ................................ ................................ ................................ . 13-4
viii S3CK225/fk225 micr ocontroller table of contents (continued) chapter 14 16-bit timer 1 overview ................................ ................................ ................................ ................................ ................. 14-1 function description ................................ ................................ ................................ ................................ 14-1 timer 1 control register (t1con) ................................ ................................ ................................ .. 14-2 block diagram ................................ ................................ ................................ ................................ . 14-3 chapter 15 8-bit timer 2 overview ................................ ................................ ................................ ................................ ................. 15-1 function description ................................ ................................ ................................ ........................ 15-2 timer 2 control register (t2con) ................................ ................................ ................................ .. 15-3 block diagram ................................ ................................ ................................ ................................ . 15-4 chapter 16 8-bit timer 3 overview ................................ ................................ ................................ ................................ ................. 16-1 timer 3 pulse width calculations ................................ ................................ ................................ .... 16-4 chapter 17 serial i/o interface overview ................................ ................................ ................................ ................................ ................. 17-1 sio control register (siocon) ................................ ................................ ................................ ............... 17-2 sio pre-scaler register (siops) ................................ ................................ ................................ ............ 17-2 block diagram ................................ ................................ ................................ ................................ ......... 17-3 serial i/o timing diagram ................................ ................................ ................................ ....................... 17-4
S3CK225/fk225 microcontroller ix table of contents (continued) chapter 18 lcd controller/driver overview ................................ ................................ ................................ ................................ ................. 18-1 lcd circuit diagram ................................ ................................ ................................ ....................... 18-2 lcd ram address area ................................ ................................ ................................ .................. 18-3 lcd control register (lcon, 60h) ................................ ................................ ................................ . 18-4 lcd port control registers (lpot1, lpot2) ................................ ................................ ......................... 18-7 lcd voltage dividing resistors ................................ ................................ ................................ ....... 18-8 lcd com/seg signals ................................ ................................ ................................ ................... 18-9 chapter 19 10-bit analog to digital converter overview ................................ ................................ ................................ ................................ ................. 19-1 function description ................................ ................................ ................................ ................................ 19-1 conversion timing ................................ ................................ ................................ .......................... 19-2 a/d converter control register (adcon) ................................ ................................ ....................... 19-2 internal reference voltage levels ................................ ................................ ................................ ... 19-3 block diagram ................................ ................................ ................................ ................................ ......... 19-3 chapter 20 d/a converter overview ................................ ................................ ................................ ................................ ................. 20-1 function description ................................ ................................ ................................ ........................ 20-1 d/a converter data register (dadatah/dadatal) ................................ ................................ ...... 20-3 chapter 21 operational amplifier overview ................................ ................................ ................................ ................................ ................. 21-1 op amp control register (opcon) ................................ ................................ ................................ 21-1
x S3CK225/fk225 micr ocontroller table of contents (continued) chapter 22 electrical data overview ................................ ................................ ................................ ................................ ................. 22-1 chapter 23 mechanical data overview ................................ ................................ ................................ ................................ ................. 23-1 chapter 24 s3fk225 flash mcu overview ................................ ................................ ................................ ................................ ................. 24-1 chapter 25 development tools overview ................................ ................................ ................................ ................................ ................. 25-1 calmshine: ide (integrated development environment) ................................ .............................. 25-1 invisible mds: in-circuit emulator ................................ ................................ ................................ ... 25-1 calmrisc8 c-compiler: calm8cc ................................ ................................ .............................. 25-1 calmrisc8 relocatable assembler: calm8asm ................................ ................................ .......... 25-1 calmrisc8 linker: calm8link ................................ ................................ ................................ .... 25-1 emulation probe board configuration ................................ ................................ ................................ ...... 25-2 external event input headers ................................ ................................ ................................ .......... 25-3 event match output headers ................................ ................................ ................................ ........... 25-3 external break input headers ................................ ................................ ................................ .......... 25-3 power selection ................................ ................................ ................................ ............................... 25-4 clock selection ................................ ................................ ................................ ................................ 25-4 vref selection ................................ ................................ ................................ ............................... 25-5 use clock setting for external clock mode ................................ ................................ .................... 25-5 sub clock setting ................................ ................................ ................................ ............................ 25-5 jp1, jp2 pin assignment ................................ ................................ ................................ ................ 25-6
S3CK225/fk225 microcontroller xi list of figures figure title page number number 1-1 top block diagram ................................ ................................ ................................ ............. 1-2 1-2 calmrisc pipeline diagram ................................ ................................ .............................. 1-3 1-3 calmrisc pipeline stream diagram ................................ ................................ .................. 1-4 1-4 block diagram ................................ ................................ ................................ .................... 1-7 1-5 pin assignment (64-qfp) ................................ ................................ ................................ ... 1-8 1-6 pin circuit type b (reset) ................................ ................................ ............................... 1-11 1-7 pin circuit type d-3 (p7) ................................ ................................ ................................ .... 1-11 1-8 pin circuit type c ................................ ................................ ................................ .............. 1-11 1-9 pin circuit type d-4 (p0) ................................ ................................ ................................ ... 1-11 1-10 pin circuit type e-4 (p1) ................................ ................................ ................................ .... 1-12 1-11 pin circuit type f-10 (p5) ................................ ................................ ................................ .. 1-12 1-12 pin circuit type h-4 ................................ ................................ ................................ ........... 1-13 1-13 pin circuit type h-14 (p2, p3, p4, p6) ................................ ................................ ............... 1-13 2-1 program memory organization ................................ ................................ ........................... 2-1 2-2 relative jump around page boundary ................................ ................................ ............... 2-2 2-3 program memory layout ................................ ................................ ................................ .... 2-3 2-4 rom code option (rcod_opt) ................................ ................................ ....................... 2-5 2-5 data memory map of calmrisc8 ................................ ................................ ...................... 2-6 2-6 data memory map of S3CK225 ................................ ................................ .......................... 2-7 3-1 bank selection by setting of grb bits and idb bit ................................ ............................. 3-3 4-1 memory map area ................................ ................................ ................................ .............. 4-1 5-1 hardware stack ................................ ................................ ................................ .................. 5-1 5-2 even and odd bank selection example ................................ ................................ ............. 5-2 5-3 stack operation with pc [19:0] ................................ ................................ ........................... 5-3 5-4 stack operation with registers ................................ ................................ ........................... 5-4 5-5 stack overflow ................................ ................................ ................................ ................... 5-5 6-1 interrupt structure ................................ ................................ ................................ .............. 6-3 6-2 interrupt structure ................................ ................................ ................................ .............. 6-4 6-3 interrupt mask register ................................ ................................ ................................ ...... 6-5 6-4 interrupt priority register ................................ ................................ ................................ .... 6-6
xii S3CK225/fk225 micr ocontroller list of figures (continued) figure title page number number 8-1 main oscillator circuit (crystal or ceramic oscillator) ................................ ......................... 8-1 8-2 main oscillator circuit (rc oscillator) ................................ ................................ ................. 8-2 8-3 sub oscillator circuit (crystal or ceramic oscillator) ................................ .......................... 8-2 8-4 system clock circuit diagram ................................ ................................ ............................ 8-3 8-5 power control register (pcon) ................................ ................................ ......................... 8-4 8-6 oscillator control register (osccon) ................................ ................................ ............... 8-4 8-7 main oscillator clock output functional block diagram ................................ ..................... 8-5 8-8 main oscillator clock output control register (clocon) ................................ .................. 8 -5 10-1 port 0 control register (p0con) ................................ ................................ ........................ 10-1 10-2 port 1 control register (p1con) ................................ ................................ ........................ 10-2 10-3 port 1 pull-up control register (p1pur) ................................ ................................ ............ 10-2 10-4 port 2 high-byte control register (p2conh) ................................ ................................ ..... 10-3 10-5 port 2 low-byte control register (p2conl) ................................ ................................ ....... 10-3 10-6 port 3 high-byte control register (p3conh) ................................ ................................ ..... 10-4 10-7 port 3 low-byte control register (p3conl) ................................ ................................ ....... 10-4 10-8 port 4 high-byte control register (p4conh) ................................ ................................ ..... 10-5 10-9 port 4 low-byte control register (p4conl) ................................ ................................ ....... 10-5 10-10 port 5 high-byte control register (p5conh) ................................ ................................ ..... 10-6 10-11 port 5 low-byte control register (p5conl) ................................ ................................ ....... 10-6 10-12 port 6 control register (p6con) ................................ ................................ ........................ 10-7 10-13 port 7 control register (p7con) ................................ ................................ ........................ 10-7 11-1 watchdog timer control register (wdtcon) ................................ ................................ ... 11-1 11-2 basic timer & watchdog timer functional block diagram ................................ ................. 11-2 12-1 watch timer circuit diagram ................................ ................................ ............................. 12-2 13-1 timer 0 control register (t0con) ................................ ................................ ..................... 13-3 13-2 timer 0 functional block diagram ................................ ................................ ...................... 13-4 13-3 timer 0 counter and data registers (t0cnth/l, t0datah/l) ................................ .......... 13-5 14-1 timer 1 control register (t1con) ................................ ................................ ..................... 14-2 14-2 timer 1 functional block diagram ................................ ................................ ...................... 14-3 14-3 timer 1 counter register (t1cnth/l) ................................ ................................ ................ 14-4 14-4 timer 1 data register (t1datah/l) ................................ ................................ .................. 14-4 15-1 timer 2 control register (t2con) ................................ ................................ ..................... 15-3 15-2 timer 2 functional block diagram ................................ ................................ ...................... 15-4
S3CK225/fk225 microcontroller xiii list of figures (continued) figure title page number number 16-1 timer 3 functional block diagram ................................ ................................ ...................... 16-2 16-2 timer 3 control register (t3con) ................................ ................................ ..................... 16-3 16-3 timer 3 data registers (t3datah/l) ................................ ................................ ................. 16-3 16-4 timer 3 output flip-flop waveforms in repeat mode ................................ ........................ 16-5 17-1 serial i/o module control registers (siocon) ................................ ................................ .. 17-2 17-2 sio pre-scaler register (siops) ................................ ................................ ........................ 17-2 17-3 sio function block diagram ................................ ................................ .............................. 17-3 17-4 serial i/o timing in transmit/receive mode(tx at falling, siocon.4=0) ........................... 17-4 17-5 serial i/o timing in transmit/receive mode(tx at rising, siocon.4=1) ............................ 17-4 18-1 lcd function diagram ................................ ................................ ................................ ....... 18-1 18-2 lcd circuit diagram ................................ ................................ ................................ .......... 18-2 18-3 lcd display data ram organization ................................ ................................ ................. 18-3 18-4 lcd port control resister1 (lpot1) ................................ ................................ .................. 18-7 18-5 lcd port control resister2 (lpot2) ................................ ................................ .................. 18-7 18-6 internal voltage dividing resistor connection ................................ ................................ .... 18-8 18-7 select/no-sel ect bias signals in static display mode ................................ ......................... 18-9 18-8 select/no-select bias signals in 1/2 duty, 1/2 bias display mode ................................ ...... 18-10 18-9 select/no-select bias signals in 1/3 duty, 1/3 bias display mode ................................ ...... 18-10 18-10 lcd signal and wave forms example in 1/2 duty, 1/2 bias display mode ........................ 18-11 18-11 lcd signals and wave forms example in 1/3 duty, 1/3 bias display mode ...................... 18-12 18-12 lcd signals and wave forms example in 1/4 duty, 1/3 bias display mode ...................... 18-13 19-1 a/d converter control register (adcon) ................................ ................................ .......... 19-2 19-2 a/d conver ter data register (addatah/addatal) ................................ ......................... 19-3 19-3 a/d converter functional block diagram ................................ ................................ ........... 19-3 19-4 recommended a/d converter circuit for highest absolute accuracy ................................ . 19-4 20-1 dac circuit diagram ................................ ................................ ................................ .......... 20-2 20-2 digital to analog converter control register (dacon) ................................ ....................... 20-2 20-3 d/a converter data register (dadatah/dadatal) ................................ ......................... 20-3
xiv S3CK225/fk225 micr ocontroller list of figures (continued) figure title page number number 21-1 op amp control register (opcon) ................................ ................................ ................... 21-1 21-2 op amp block diagram ................................ ................................ ................................ ..... 21-2 22-1 input timing for external interrupts (port 0) ................................ ................................ ........ 22-4 22-2 input timing for reset ................................ ................................ ................................ ............... 22-4 22-3 stop mode release timing when initiated by a reset ................................ .......................... 22-5 22-4 stop mode release timing initiated by interrupts ................................ ............................... 22-6 22-5 serial data transfer timing ................................ ................................ ................................ 22-8 22-6 clock timing measurement at x in ................................ ................................ .............................. 22-10 22-7 clock timing measurement at xt in ................................ ................................ ............................ 22-10 22-8 operating voltage range ................................ ................................ ................................ ... 22-12 23-1 64-pin qfp package dimensions (64-qfp-1420f) ................................ ............................ 23-1 24-1 s3fk225 pin assignments (64-qfp-1420f) ................................ ................................ ....... 24-2 25-1 emulation probe board configuration ................................ ................................ ................. 25-2
S3CK225/fk225 microcontroller xv list of tables table title page number nu mber 1-1 pin descriptions ................................ ................................ ................................ ................. 1-9 3-1 general and special purpose registers ................................ ................................ .............. 3-1 3-2 status register 0 configuration ................................ ................................ ........................... 3-3 3-3 status register 1: sr1 ................................ ................................ ................................ ....... 3-4 4-1 registers ................................ ................................ ................................ ............................ 4-2 6-1 exceptions ................................ ................................ ................................ .......................... 6-1 7-1 instruction notation conventions ................................ ................................ ........................ 7-1 7-2 overall instruction set map ................................ ................................ ................................ 7-2 7-3 instruction encoding ................................ ................................ ................................ ........... 7-4 7-4 index code information (?idx?) ................................ ................................ ............................ 7-7 7-5 index modification code information (?mod?) ................................ ................................ ...... 7-7 7-6 condition code information (?cc?) ................................ ................................ ....................... 7-7 7-7 ?aluop1? code information ................................ ................................ ................................ 7-8 7-8 ?aluop2? code information ................................ ................................ ................................ 7-8 7-9 ?modop1? cod e information ................................ ................................ .............................. 7-8 12-1 watch timer control register (wtcon): 8-bit r/w ................................ .......................... 12-1 18-1 lcd control register (lcon) organization ................................ ................................ ........ 18-4 18-2 relationship of lcon.0 and lmod.3 bit settings ................................ .............................. 18-4 18-3 lcd clock signal (lcdck) frame frequency ................................ ................................ .... 18-5 18-4 lcd mode control register (lmod) organization, 4ch ................................ ..................... 18-6 18-5 maximum number of display digits per duty cycle ................................ ............................ 18-6 20-1 dadata setting to generate analog voltage ................................ ................................ .... 20-3
xvi S3CK225/fk225 micr ocontroller list of tables (continued) table title page number number 22-1 absolute maximum ratings ................................ ................................ ................................ 22-1 22-2 d.c. electrical characteristics ................................ ................................ ............................ 22-1 22-3 a.c. electrical characteristics ................................ ................................ ............................. 22-4 22-4 input/output capacitance ................................ ................................ ................................ ... 22-5 22-5 data retention supply voltage in stop mode ................................ ................................ ..... 22-5 22-6 a/d converter electrical characteristics ................................ ................................ ............. 22-7 22-7 d/a converter electrical characteristics ................................ ................................ ............. 22-7 22-8 synchronous sio electrical characteristics ................................ ................................ ........ 22-8 22-9 main oscillator frequency (f osc1 ) ................................ ................................ ...................... 22-9 22-10 main oscillator clock stabilization time (t st1 ) ................................ ................................ .. 22-9 22-11 sub oscillator frequency (f osc2 ) ................................ ................................ ........................ 22-10 22-12 sub oscillator (crystal) start up time (t st2 ) ................................ ................................ ....... 22-11 22-13 op amplifier characteristics ................................ ................................ ............................... 22-11 24-1 descriptions of pins used to read/write the flash rom ................................ ................. 24-3
S3CK225/fk225 microcontroller xvii list of programming tips description page number chapter 6: exceptions interrupt programming tip 1 ................................ ................................ ................................ .................... 6-7 interrupt programming tip 2 ................................ ................................ ................................ .................... 6-8 chapter 16: 8-bit timer 3 to generate 38 khz, 1/3duty signal through p7.2 ................................ ................................ ............................. 16-6 to generate a one pulse signal through p7.2 ................................ ................................ ................................ .... 16-7

S3CK225/fk225 microcontroller xix list of instruction descriptions instruction full instruction name page mnemonic number adc add with carry ................................ ................................ ................................ ....... 7-30 add a dd ................................ ................................ ................................ ........................ 7-31 and bit-wise and ................................ ................................ ................................ .......... 7-32 and sr0 bit-wise and with sr0 ................................ ................................ ........................... 7-33 bank bank selection ................................ ................................ ................................ ....... 7-34 bitc bit complement ................................ ................................ ................................ ..... 7-35 bitr bit reset ................................ ................................ ................................ ................ 7-36 bits bit set ................................ ................................ ................................ .................... 7-37 bitt bit test ................................ ................................ ................................ .................. 7-38 bmc/bms tf bit clear/set ................................ ................................ ................................ ....... 7-39 call conditional subroutine call (pseudo instruction) ................................ .................... 7-40 calls call subroutine ................................ ................................ ................................ ...... 7-41 cld load into coprocessor ................................ ................................ ........................... 7-42 cld load from coprocessor ................................ ................................ .......................... 7-43 com 1's or bit-wise complement ................................ ................................ .................... 7-44 com2 2's complement ................................ ................................ ................................ ..... 7-45 comc bit-wise complement with carry ................................ ................................ ............ 7-46 cop coprocessor ................................ ................................ ................................ ........... 7-47 cp compare ................................ ................................ ................................ ................ 7-48 cpc compare with carry ................................ ................................ ............................... 7-49 dec decrement ................................ ................................ ................................ ............. 7-50 decc decrement with carry ................................ ................................ ............................ 7-51 di disable interrupt (pseudo instruction) ................................ ................................ .... 7-52 ei enable interrupt (pseudo instruction) ................................ ................................ .... 7-53 idle idle operation (pseudo instruction) ................................ ................................ ....... 7-54 inc increment ................................ ................................ ................................ ............... 7-55 incc increment with carry ................................ ................................ .............................. 7-56 iret retu rn from interrupt handling ................................ ................................ ............... 7-57 jnzd jump not zero with delay slot ................................ ................................ ............... 7-58 jp conditional jump (pseudo instruction) ................................ ................................ .. 7-59 jr conditional jump relative ................................ ................................ ..................... 7-60 lcall conditional subroutine call ................................ ................................ .................... 7-61 ld adr:8 load into memory ................................ ................................ ................................ .. 7-62
xx S3CK225/fk225 micr ocontroller list of instruction descriptions (continued) instruction full instruction name page mnemonic number ld @idm load into memory indexed ................................ ................................ ..................... 7-63 ld load register ................................ ................................ ................................ ......... 7-64 ld load gpr:bankd, gpr:banks ................................ ................................ ................ 7-65 ld load gpr, tbh/tbl ................................ ................................ .............................. 7-66 ld load tbh/tbl, gpr ................................ ................................ .............................. 7-67 ld spr load spr ................................ ................................ ................................ ......................... 7-68 ld spr0 load spr0 immediate ................................ ................................ ........................... 7-69 ldc load code ................................ ................................ ................................ ............. 7-70 ljp conditional jump ................................ ................................ ................................ ... 7-71 llnk linked subroutine call conditional ................................ ................................ ......... 7-72 lnk linked subroutine call (pseudo instruction) ................................ .......................... 7-73 lnks linked subroutine call ................................ ................................ ........................... 7-74 lret return from linked subroutine call ................................ ................................ ........ 7-75 nop no operation ................................ ................................ ................................ .......... 7-76 or bit-wise or ................................ ................................ ................................ ............ 7-77 or sr0 bit-wise or with sr0 ................................ ................................ ............................. 7-78 pop pop ................................ ................................ ................................ ....................... 7-79 pop pop to register ................................ ................................ ................................ ..... 7-80 push push register ................................ ................................ ................................ ......... 7-81 ret return from subroutine ................................ ................................ .......................... 7-82 rl rotate left ................................ ................................ ................................ ............. 7-83 rlc rotate left with carry ................................ ................................ ............................ 7-84 rr rotate right ................................ ................................ ................................ ........... 7-85 rrc rotate right with carry ................................ ................................ .......................... 7-86 sbc subtract with carry ................................ ................................ ................................ . 7-87 sl shift left ................................ ................................ ................................ ................ 7-88 sla shift left arithmetic ................................ ................................ ............................... 7-89 sr shift right ................................ ................................ ................................ .............. 7-90 sra shift right arithmetic ................................ ................................ ............................. 7-91 stop stop operation (pseudo instruction) ................................ ................................ ...... 7-92 sub subtract ................................ ................................ ................................ ................. 7-93 swap swap ................................ ................................ ................................ ...................... 7-94 sys system ................................ ................................ ................................ ................... 7-95 tm test multiple bits ................................ ................................ ................................ .... 7-96 xor exclusive or ................................ ................................ ................................ ......... 7-97
S3CK225/fk225 produ ct overview 1- 1 1 product overview overview the S3CK225/fk225 single-chip cmos microcontroller is designed for high performance using samsung's new 8-bit cpu core, calmrisc. calmrisc is an 8-bit low power risc microcontroller. its basic architecture follows harvard style, that is, it has separate program memory and data memory. both instruction and data can be fetched simultaneously without causing a stall, using separate paths for memory access. represented below is the top block diagram of the calmrisc microcontroller.
product overview s 3ck225/fk225 1- 2 bbus[7:0] 20 program memory address generation unit pc[19:0] hardware stack hs[0] hs[15] 8 8 r0 r3 r1 r2 alu abus[7:0] alul alur pa[19:0] pd[15:0] idl0 idl1 sr0 sr1 ilh ilx ill spr idh do[7:0] di[7:0] gpr data memory address generation unit da[15:0] 20 flag rbus tbh tbl figure 1-1. top block diagram
S3CK225/fk225 produ ct overview 1- 3 the calmrisc building blocks consist of: ? an 8-bit alu ? 16 general purpose registers (gpr) ? 11 special purpose registers (spr) ? 16-level hardware stack ? program memory address generation unit ? data memory address generation unit sixteen gprs are grouped into four banks (bank0 to bank3), and each bank has four 8-bit registers (r0, r1, r2, and r3). sprs, designed for special purposes, include status registers, link registers for branch-link instructions, and data memory index registers. the data memory address generation unit provides the data memory address (denoted as da[15:0] in the top block diagram) for a data memory access instruction. data memory contents are accessed through di[7:0] for read operations and do[7:0] for write operations. the program memory address generation unit contains a program counter, pc[19:0], and supplies the program memory address through pa[19:0] and fetches the corresponding instruction through pd[15:0] as the result of the program memory access. calmrisc has a 16-level hardware stack for low power stack operations as well as a temporary storage area. instruction fetch (if) instruction decode/ data memory access (id/mem) execution/writeback (exe/wb) figure 1-2. calmrisc pipeline diagram calmrisc has a 3-stage pipeline as described below: as can be seen in the pipeline scheme, calmrisc adopts a register-memory instruction set. in other words, data memory where r is a gpr can be one operand of an alu instruction as shown below: the first stage (or cycle) is the instruction fetch stage (if for short), where the instruction pointed by the program counter, pc[19:0] , is read into the instruction register (ir for short). the second stage is the instruction decode and data memory access stage (id/mem for short), where the fetched instruction (stored in ir) is decoded and data memory access is performed, if necessary. the final stage is the execute and write-back stage (exe/wb), where the required alu operation is executed and the result is written back into the destination registers. since calmrisc instructions are pipelined, the next instruction fetch is not postponed until the current instruction is completely finished but is performed immediately after completing the current instruction fetch. the pipeline stream of instructions is illustrated in the following diagram.
product overview s 3ck225/fk225 1- 4 exe/wb if if if if if if if id/mem id/mem id/mem id/mem id/mem id/mem exe/wb exe/wb exe/wb exe/wb exe/wb / 1 / 2 / 3 / 4 / 6 / 5 figure 1-3. calmrisc pipeline stream diagram most calmrisc instructions are 1-word instructions, while same branch instructions such as long ?call? and ?jp? instructions are 2-word instructions. in figure 1-3, the instruction, i4 , is a long branch instruction, and it takes two clock cycles to fetch the instruction. as indicated in the pipeline stream, the number of clocks per instruction (cpi) is 1 except for long branches, which take 2 clock cycles per instruction.
S3CK225/fk225 produ ct overview 1- 5 features cpu calmrisc core (8-bit risc architecture) memory rom: 8k-word (16k-byte) ram: 384-byte (excluding lcd data ram) stack size: maximum 16 word-level 48 i/o pins 12 normal i/o pins 36 i/o pins sharing with lcd signals basic timer overflow signal makes a system reset watchdog function 16-bit timer/counter 0 programmable 16-bit timer interval, capture, pwm mode match, overflow interrupt 16-bit timer/counter 1 programmable 16-bit timer match interrupt generator 8-bit timer/counter 2 programmable 8-bit timer interval, pwm mode match, overflow interrupt 8-bit timer/counter 3 programmable 8-bit timer match interrupt/carrier frequency generator watch timer real-time and interval time measurement clock generation for lcd four frequency outputs for buzzer sound (0.5/1/2/4 khz at 32.768 khz) lcd controller/driver 32 segments and 4 common terminals static, 1/2 duty, 1/3 duty, 1/4 duty internal resistor circuit for lcd bias 8-bit serial i/o interface 8-bit transmit/receive mode 8-bit receive mode lsb-first/msb-first transmission selectable internal/external clock source a/d converter eight analog input channels 25 m s conversion speed at 8 mhz 10-bit conversion resolution operating voltage: 2.7 v to 5.5 v d/a converter one analog output channel 10-bit conversion resolution (r-2r) operating voltage: 2.7 v to 5.5 v oscillation sources crystal, ceramic, rc for main clock crystal for sub clock main clock frequency: 0.4?8 mhz sub clock frequency: 32.768 khz cpu clock divider circuit (divided by 1, 2, 4, 8, 16, 32, 64 or 128)
product overview s 3ck225/fk225 1- 6 features (continued) two power-down modes idle (only cpu clock stops) stop (system clock stops) interrupts 2 vectors, 13 interrupts instruction execution times 125 ns at 8 mhz (main clock) 30.5 m s at 32.768 khz (sub clock) operating temperature range - 25 c to 85 c operating voltage range 2.0 v to 5.5 v at 2 mhz (2mips) 2.4 v to 5.5 v at 4 mhz (4mips) 3.0 v to 5.5 v at 8 mhz (8mips) two amplifiers microphone and filter package type 64-pin qfp-1420f
S3CK225/fk225 produ ct overview 1- 7 block diagram reset osc, reset 16-bit timer/ counter 0 10-bit a/d converter p0.0-p0.3/ int0-int3 i/o port 1 x in , xt in 16-bit timer/ counter 1 8-bit timer/ counter 2 8-bit timer/ counter 3 i/o port 0 i/o port 5 i/o port 7 t0out/t0pwm/p7.1 t0clk/p7.2 t0cap/p7.3 t3pwm/p7.2 p1.0/buz p1.1/so p1.2/sck p1.3/si av ref av ss p5.0-p5.7/ad0-ad7/ seg24-seg31 p7.0/t2out/t2pwm p7.1/t2clk/t0out/t0pwm p7.2/t0clk/t3pwm p7.3/t0cap/clkout dao calm8 risc cpu 384-byte register file 16k-byte rom basic timer watch timer x out , xt out buz/p1.0 p4.0-p4.7/ seg16-seg23 t2out/t2pwm/p7.0 t2clk/p7.1 10-bit d/a converter serial i/o port p6.0-p6.3/ com0-com3 lcd driver i/o port 2 i/o port 3 i/o port 4 i/o port 6 two amplifiers i/o port and interrupt control com0-com3/ p6.0-p6.3 seg0-seg31/ p2.0-p5.7 so/p1.1 sck/p1.2 si/p1.3 p2.0-p2.7/ seg0-seg7 p3.0-p3.7/ seg8-seg15 ad0-ad7/p5.0-p5.7 filin, micin filout, micout, vref figure 1-4. block diagram
product overview s 3ck225/fk225 1- 8 pin assignment com0/p6.0 com1/p6.1 com2/p6.2 com3/p6.3 p7.0/t2out/t2pwm p7.1/t2clk/t0out/t0pwm p7.2/t0clk/t3pwm p7.3/t0cap/clkout v dd v ss x out x in test xt in xt out reset dao filin filout p2.0/seg0 p2.1/seg1 p2.2/seg2 p2.3/seg3 p2.4/seg4 p2.5/seg5 p2.6/seg6 p2.7/seg7 p3.0/seg8 p3.1/seg9 p3.2/seg10 p3.3/seg11 p3.4/seg12 vref micin micout p0.0/int0 p0.1/int1 p0.2/int2 p0.3/int3 p1.0/buz p1.1/so p1.2/sck p1.3/si avref avss p3.5/seg13 p3.6/seg14 p3.7/seg15 p4.0/seg16 p4.1/seg17 p4.2/seg18 p4.3/seg19 p4.4/seg20 p4.5/seg21 p4.6/seg22 p4.7/seg23 p5.0/seg24/ad0 p5.1/seg25/ad1 p5.2/seg26/ad2 p5.3/seg27/ad3 p5.4/seg28/ad4 p5.5/seg29/ad5 p5.6/seg30/ad6 p5.7/seg31/ad7 S3CK225/fk225 (64-qfp-1420f) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 figure 1-5. pin assignment (64-qfp)
S3CK225/fk225 produ ct overview 1- 9 pin descriptions table 1-1. pin descriptions pin names pin type pin description circuit type pin numbers share pins p0.0 p0.1 p0.2 p0.3 i/o i/o port with bit programmable pins; schmitt trigger input or output mode selected by software; software assignable pull-up resistors. (with noise filter and interrupt control). d-4 23 24 25 26 int0 int1 int2 int3 p1.0 p1.1 p1.2 p1.3 i/o i/o port with bit programmable pins; schmitt trigger input or output mode selected by software; open-drain output mode can be selected by software; software assignable pull-up resistors. e-4 27 28 29 30 buz so sck si p2.0-p2.7 i/o i/o port with bit programmable pins; push-pull or open-drain output and input with software assignable pull-up resistors. h-14 64-57 seg0-seg7 p3.0-p3.7 i/o have the same characteristic as port 2 h-14 56-49 seg8-seg15 p4.0-p4.7 i/o have the same characteristic as port 2 h-14 48-41 seg16-seg23 p5.0-p5.7 i/o i/o port with bit programmable pins; normal input or output mode selected by software; software assignable pull-up resistors. f-10 40-33 ad0-ad7/ seg24-seg31 p6.0-p6.3 i/o have the same characteristic as port 2 h-14 1-4 com0-com3 p7.0 p7.1 p7.2 p7.3 i/o i/o port with bit programmable pins; schmitt trigger input or push-pull output with software assignable pull-up resistors. d-3 5 6 7 8 t2out/t2pwm t2clk/t0out/t0pwm t0clk/t3pwm t0cap/clkout ad0-ad7 i/o a/d converter analog input channels f-10 40-33 p5.0-p5.7/ seg24-seg31 av ref ? a/d converter reference voltage ? 31 ? av ss ? a/d converter ground ? 32 ? int0-int3 i/o external interrupt input pins d-4 23-26 p0.0-p0.3 reset i system reset pin b 16 ? test i test signal input (must be connected to v ss ) ? 13 ?
product overview s 3ck225/fk225 1- 10 table 1-1. pin descriptions (continued) pin names pin type pin description circuit type pin numbers share pins v dd , v ss ? main power supply and ground ? 9, 10 ? x out , x in ? main oscillator pins ? 11, 12 ? xt out , xt in ? sub oscillator pins ? 15, 14 ? so, sck, si i/o serial i/o interface clock signal e-4 28-30 p1.1-p1.3 t3pwm i/o timer 3 pwm output d-3 7 p7.2 t2out/t2pwm i/o timer 2 output and pwm output d-3 5 p7.0 t2clk i/o timer 2 external clock input d-3 6 p7.1 t0clk i/o timer 0 external clock input d-3 7 p7.2 t0cap i/o timer 0 capture input d-3 8 p7.3 t0out/t0pwm i/o timer 0 output and pwm output d-3 6 p7.1 com0-com3 i/o lcd common signal output h-14 1-4 p6.0-p6.3 seg0-seg7 i/o lcd segment output h-14 64-57 p2.0-p2.7 seg8-seg15 i/o lcd segment output h-14 56-49 p3.0-p3.7 seg16-seg23 i/o lcd segment output h-14 48-41 p4.0-p4.7 seg24-seg31 i/o lcd segment output h-14 40-33 p5.0-p5.7/ ad0-ad7 buz i/o 0.5, 1, 2 or 4 khz frequency output for buzzer sound with 4.19 mhz main clock or 32768 hz sub clock e-4 27 p1.0 clkout i/o main oscillator clock output d-3 8 p7.3 dao ? da converter output ? 17 ? filin, filout ? filter amp input and output ? 18, 19 ? micin, micout ? mic amp input and output ? 21, 22 ? vref ? reference voltage output for filter amp and mic amp ? 20 ?
S3CK225/fk225 produ ct overview 1- 11 pin circuits in v dd figure 1-6. pin circuit type b ( reset reset ) i/o output disable data circuit type c pull-up enable v dd p-channel figure 1-7. pin circuit type d-3 (p7) p-ch n-ch v dd out output disable data figure 1-8. pin circuit type c i/o output disable data circuit type c pull-up enable v dd noise filter ext. int input normal figure 1-9. pin circuit type d-4 (p0)
product overview s 3ck225/fk225 1- 12 v dd output disable data pull-up resistor v dd i/o p-ch n-ch open drain enable figure 1-10. pin circuit type e-4 (p1) i/o output disable data pull-up enable v dd adc enable to adc data circuit type h-4 seg lcd en circuit type c figure 1-11. pin circuit type f-10 (p5)
S3CK225/fk225 produ ct overview 1- 13 out seg v dd v lc1 v lc0 output disable figure 1-12. pin circuit type h-4 v dd output disable data pull-up enable v dd i/o p-ch n-ch open drain enable circuit type h-4 seg lcd out enable figure 1-13. pin circuit type h-14 (p2, p3, p4, p6)
product overview s 3ck225/fk225 1- 14 notes
S3CK225/fk225 addre ss spaces 2- 1 2 address spaces overview calmrisc has 20-bit program address lines, pa[19:0] , which supports up to 1m words of program memory. the 1m word program memory space is divided into 256 pages and each page is 4k word long as shown in the figure 2-1. the upper 8 bits of the program counter, pc[19:12], points to a specific page and the lower 12 bits, pc[11:0], specify the offset address of the page. calmrisc also has 16-bit data memory address lines, da[15:0], which supports up to 64k bytes of data memory. the 64k byte data memory space is divided into 256 pages and each page has 256 bytes. the upper 8 bits of the data address, da[15:8], points to a specific page and the lower 8 bits, da[7:0], specify the offset address of the page. program memory (rom) 000h fffh 256 page 1 mword 4 kword fffh 000h figure 2-1. program memory organization
address spaces s3c k225/fk225 2- 2 for example, if pc[19:0] = 5f79ah, the page index pointed to by pc is 5fh and the offset in the page is 79ah. if the current pc[19:0] = 5efffh and the instruction pointed to by the current pc, i.e., the instruction at the address 5efffh is not a branch instruction, the next pc becomes 5e000h, not 5f000h. in other words, the instruction sequence wraps around at the page boundary, unless the instruction at the boundary (in the above example, at 5efffh) is a long branch instruction. the only way to change the program page is by long branches (lcall, llnk, and ljp), where the absolute branch target address is specified. for example, if the current pc[19:0] = 047ach (the page index is 04h and the offset is 7ach) and the instruction pointed to by the current pc, i.e., the instruction at the address 047ach, is "ljp a507fh" (jump to the program address a507fh), then the next pc[19:0] = a507fh, which means that the page and the offset are changed to a5h and 07fh, respectively. on the other hand, the short branch instructions cannot change the page indices. suppose the current pc is 6fffeh and its instruction is "jr 5h" (jump to the program address pc + 5h). then the next instruction address is 6f003h, not 70003h. in other words, the branch target address calculation also wraps around with respect to a page boundary. this situation is illustrated below: 000h 001h 002h 003h 004h 005h ffeh fffh page 6fh jr 5h figure 2-2. relative jump around page boundary programmers do not have to manually calculate the offset and insert extra instructions for a jump instruction across page boundaries. the compiler and the assembler for calmrisc are in charge of producing appropriate codes for it.
S3CK225/fk225 addre ss spaces 2- 3 00000h fffffh vector and option area ~ ~ ~ ~ 00020h 0001fh program memory area (4k words x 256 page = 1 mword) 8k words (16k bytes) note: for S3CK225, total size of program memory area is 8k words (16k bytes). 1fffh figure 2-3. program memory layout from 00000h to 00004h addresses are used for the vector address of exceptions, and 0001eh, 0001fh are used for the option only. aside from these addresses others are reserved in the vector and option area. program memory area from the address 00020h to fffffh can be used for normal programs. the program memory size of S3CK225 is 8k word (16k byte), so from the address 00020h to 1fffh are the program memory area.
address spaces s3c k225/fk225 2- 4 rom code option (rcod_opt) just after power on, the rom data located at 0001eh and 0001fh is used as the rom code option. S3CK225 has rom code options like the reset value of basic timer and watchdog timer enable. for example, if you program as below: rcod_opt 1eh, 0x0000 rcod_opt 1fh, 0xbfff ? fxx/32 is used as reset value of basic timer (by bit.14, 13, 12) ? watchdog timer is enabled (by bit.11) if you don't program any values in these option areas, then the default value is "1". in these cases, the address 0001eh would be the value of "ffffh".
S3CK225/fk225 addre ss spaces 2- 5 rom_code option (rcod_opt) rom address: 0001fh reset value of basic timer clock selection bits (wdtcon.6, .5, .4): 000 = fxx/2 001 = fxx/4 010 = fxx/16 011 = fxx/32 100 = fxx/128 101 = fxx/256 110 = fxx/1024 111 = fxx/2048 not used watchdog timer enable selection bit: 0 = disable wdt 1 = enable wdt .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used .15 .14 .13 .12 .11 .10 .9 .8 msb lsb rom address: 0001eh .15 .14 .13 .12 .11 .10 .9 .8 msb lsb not used not used figure 2-4. rom code option (rcod_opt)
address spaces s3c k225/fk225 2- 6 data memory organization the total data memory address space is 64k bytes, addressed by da[15:0], and divided into 256 pages, each page consists of 256 bytes as shown below. 00h ffh 256 page 64k-byte 256-byte 00h ffh 2 page figure 2-5. data memory map of calmrisc8 the data memory page is indexed by spr and idh. in data memory index addressing mode, 16-bit data memory address is composed of two 8-bit sprs, idh[7:0] and idl0[7:0] (or idh[7:0] and idl1[7:0]). idh[7:0] points to a page index, and idl0[7:0] (or idl1[7:0]) represents the page offset. in data memory direct addressing mode, an 8-bit direct address, adr[7:0], specifies the offset of the page pointed to by idh[7:0] (see the details for direct addressing mode in the instruction sections). unlike the program memory organization, data memory address does not wrap around. in other words, data memory index addressing with modification performs an addition or a subtraction operation on the whole 16-bit address of idh[7:0] and idl0[7:0] (or idl1[7:0]) and updates idh[7:0] and idl0[7:0] (or idl1[7:0]) accordingly. suppose idh[7:0] is 0fh and idl0[7:0] is fch and the modification on the index registers, idh[7:0] and idl0[7:0], is increment by 5h, then, after the modification (i.e., 0ffch + 5 = 1001h), idh[7:0] and idl0[7:0] become 10h and 01h, respectively.
S3CK225/fk225 addre ss spaces 2- 7 the S3CK225 has 400 bytes of data register address from 0080h to 020fh. the area from 0000h to 007fh is for peripheral control, and lcd ram area is from 0200h to 020fh. data memory control register page 0 80h ffh in byte 7fh 00h 8-bit page1 data memory for lcd display 0fh 00h page 2 figure 2-6. data memory map of S3CK225
address spaces s3c k225/fk225 2- 8 notes
S3CK225/fk225 regis ters 3- 1 3 registers overview the registers of calmrisc are grouped into 2 parts: general purpose registers and special purpose registers. table 3-1. general and special purpose registers registers mnemonics description reset value general purpose r0 general register 0 unknown registers (gpr) r1 general register 1 unknown r2 general register 2 unknown r3 general register 3 unknown special purpose group 0 (spr0) idl0 lower byte of index register 0 unknown registers (spr) idl1 lower byte of index register 1 unknown idh higher byte of index register unknown sr0 status register 0 00h group 1 (spr1) ilx instruction pointer link register for extended byte unknown ilh instruction pointer link register for higher byte unknown ill instruction pointer link register for lower byte unknown sr1 status register 1 unknown gpr ' s can be used in most instructions such as alu instructions, stack instructions, load instructions, etc (see the instruction set sections). from the programming standpoint, they have almost no restriction whatsoever. calmrisc has 4 banks of gpr ' s and each bank has 4 registers, r0, r1, r2, and r3. hence, 16 gpr ' s in total are available. the gpr bank switching can be done by setting an appropriate value in sr0[4:3] (see sr0 for details). the alu operations between gpr ' s from different banks are not allowed. spr ' s are designed for their own dedicated purposes. they have some restrictions in terms of instructions that can access them. for example, direct alu operations cannot be performed on spr ' s. however, data transfers between a gpr and an spr are allowed and stack operations with spr ' s are also possible (see the instruction sections for details).
registers S3CK225/ fk225 3- 2 index registers: idh, idl0 and idl1 idh in concatenation with idl0 (or idl1) forms a 16-bit data memory address. note that calmrisc ' s data memory address space is 64 k byte (addressable by 16-bit addresses). basically, idh points to a page index and idl0 (or idl1) corresponds to an offset of the page. like gpr ' s, the index registers are 2-way banked. there are 2 banks in total, each of which has its own index registers, idh, idl0 and idl1. the banks of index registers can be switched by setting an appropriate value in sr0[2] (see sr0 for details). normally, programmers can reserve an index register pair, idh and idl0 (or idl1), for software stack operations. link registers: ilx, ilh and ill the link registers are specially designed for link-and-branch instructions (see lnk and lret instructions in the instruction sections for details). when an lnk instruction is executed, the current pc[19:0] is saved into ilx, ilh and ill registers, i.e., pc[19:16] into ilx[3:0], pc[15:8] into ilh [7:0], and pc[7:0] into ill[7:0], respectively. when an lret instruction is executed, the return pc value is recovered from ilx, ilh, and ill, i.e., ilx[3:0] into pc[19:16], ilh[7:0] into pc[15:8] and ill[7:0] into pc[7:0], respectively. these registers are used to access program memory by ldc/ldc+ instructions. when an ldc or ldc+ instruction is executed, the (code) data residing at the program address specified by ilx:ilh:ill will be read into tbh:tbl. ldc+ also increments ill after accessing the program memory. there is a special core input pin signal, np64kw , which is reserved for indicating that the program memory address space is only 64 k word. by grounding the signal pin to zero, the upper 4 bits of pc, pc[19:16], is deactivated and therefore the upper 4 bits, pa[19:16], of the program memory address signals from calmrisc core are also deactivated. by doing so, power consumption due to manipulating the upper 4 bits of pc can be totally eliminated (see the core pin description section for details). from the programmer ? s standpoint, when np64kw is tied to the ground level, then pc[19:16] is not saved into ilx for lnk instructions and ilx is not read back into pc[19:16] for lret instructions. therefore, ilx is totally unused in lnk and lret instructions when np64kw = 0.
S3CK225/fk225 registers 3- 3 status register 0: sr0 sr0 is mainly reserved for system control functions and each bit of sr0 has its own dedicated function. table 3-2. status register 0 configuration flag name bit description eid 0 data memory page selection in direct addressing ie 1 global interrupt enable idb 2 index register banking selection grb[1:0] 4,3 gpr bank selection exe 5 stack overflow/underflow exception enable ie0 6 interrupt 0 enable ie1 7 interrupt 1 enable sr0[0] (or eid) selects which page index is used in direct addressing. if eid = 0, then page 0 (page index = 0) is used. otherwise ( eid = 1), idh of the current index register bank is used for page index. sr0[1] (or ie) is the global interrupt enable flag. as explained in the interrupt/exception section, calmrisc has 3 interrupt sources (non- maskable interrupt, interrupt 0, and interrupt 1) and 1 stack exception. both interrupt 0 and interrupt 1 are masked by setting sr0[1] to 0 (i.e., ie = 0). when an interrupt is serviced, the global interrupt enable flag ie is automatically cleared. the execution of an iret instruction (return from an interrupt service routine) automatically sets ie = 1. sr0[2] (or idb) and sr0[4:3] (or grb[1:0]) selects an appropriate bank for index registers and gpr's, respectively as shown below: r3 r0 r2 r1 r3 r0 r2 r1 r3 r0 r2 r1 r3 r0 r2 r1 idh idl0 idl1 idh idl0 idl1 bank 0 bank 1 bank 2 bank 3 11 10 01 00 grb [1:0] 0 1 idb figure 3-1. bank selection by setting of grb bits and idb bit sr0[5] (or exe) enables the stack exception, that is, the stack overflow/underflow exception. if exe = 0, the stack exception is disabled. the stack exception can be used for program debugging in the software development stage. sr0[6] (or ie0) and sr0[7] (or ie1) are enabled, by setting them to 1. even though ie0 or ie1 are enabled, the interrupts are ignored (not serviced) if the global interrupt enable flag ie is set to 0.
registers S3CK225/ fk225 3- 4 status register 1: sr1 sr1 is the register for status flags such as alu execution flag and stack full flag. table 3-3. status register 1: sr1 flag name bit description c 0 carry flag v 1 overflow flag z 2 zero flag n 3 negative flag sf 4 stack full flag ? 5,6,7 reserved sr1[0] (or c) is the carry flag of alu executions. sr1[1] (or v) is the overflow flag of alu executions. it is set to 1 if and only if the carry-in into the 8-th bit position of addition/subtraction differs from the carry-out from the 8-th bit position. sr1[2] (or z) is the zero flag, which is set to 1 if and only if the alu result is zero. sr1[3] (or n) is the negative flag. basically, the most significant bit (msb) of alu results becomes n flag. note a load instruction into a gpr is considered an alu instruction. however, if an alu instruction touches the overflow flag (v) like add, sub, cp, etc , n flag is updated as exclusive-or of v and the msb of the alu result. this implies that even if an alu operation results in overflow, n flag is still valid. sr1[4] (or sf) is the stack overflow flag. it is set when the hardware stack is overflowed or under flowed. programmers can check if the hardware stack has any abnormalities by the stack exception or testing if sf is set (see the hardware stack section for great details). note when an interrupt occurs, sr0 and sr1 are not saved by hardware, so sr0, and sr1 register values must be saved by software.
S3CK225/fk225 memor y map 4- 1 4 memory map overview to support the control of peripheral hardware, the address for peripheral control registers are memory-mapped to page 0 of the ram. memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location. in this section, detailed descriptions of the control registers are presented in an easy-to-read format. you can use this section as a quick-reference source when writing application programs. this memory area can be accessed with the whole method of data memory access. ? if sr0 bit 0 is "0" then the accessed register area is always page 0. ? if sr0 bit 0 is "1" then the accessed register page is controlled by the proper idh register's value. so if you want to access the memory map area, clear the sr0.0 and use the direct addressing mode. this method is used for most cases. this control register is divided into five areas. here, the system control register area is same in every device. 7fh 00h control register system control register area port data register area peripheral control register (4 x 8) peripheral control register ( 1x 16 or 2 x 8) 0fh 10h port control register area (4 x 8) 1fh 20h 3fh 40h 6fh 70h standard exhortative area standard area figure 4-1. memory map area
memory map S3CK225 /fk225 4- 2 table 4-1. registers register name mnemonic decimal hex reset r/w locations 18h-1fh are not mapped port 7 data register p7 23 17h 00h r/w port 6 data register p6 22 16h 00h r/w port 5 data register p5 21 15h 00h r/w port 4 data register p4 20 14h 00h r/w port 3 data register p3 19 13h 00h r/w port 2 data register p2 18 12h 00h r/w port 1 data register p1 17 11h 00h r/w port 0 data register p0 16 10h 00h r/w locations 0eh-0fh are not mapped. watchdog timer control register wdtcon 13 0dh x0h r/w basic timer counter btcnt 12 0ch 00h r interrupt id register 1 iir1 11 0bh ? r/w interrupt priority register 1 ipr1 10 0ah ? r/w interrupt mask register 1 imr1 9 09h 00h r/w interrupt request register 1 irq1 8 08h ? r interrupt id register 0 iir0 7 07h ? r/w interrupt priority register 0 ipr0 6 06h ? r/w interrupt mask register 0 imr0 5 05h 00h r/w interrupt request register 0 irq0 4 04h ? r oscillator control register osccon 3 03h 00h r/w power control register pcon 2 02h 04h r/w locations 00h-01h are not mapped. notes: 1. '?' means undefined. 2. if you want to clear the bit of irqx, then write the number that you want to clear to iirx. for example, when clear irq0.4 then ld rx, #04h and ld iir0, rx.
S3CK225/fk225 memor y map 4- 3 table 4-1. registers (continued) register name mnemonic decimal hex reset r/w timer 2 counter t2cnt 82 52h ? r timer 2 data register t2data 81 51h ffh r/w timer 2 control register t2con 80 50h 00h r/w locations 4dh-4fh are not mapped timer 1 counter (low byte) t1cntl 76 4ch ? r timer 1 counter (high byte) t1cnth 75 4bh ? r timer 1 data register (low byte) t1datal 74 4ah ffh r/w timer 1 data register (high byte) t1datah 73 49h ffh r/w timer 1 control register t1con 72 48h 00h r/w locations 45h-47h are not mapped timer 0 counter (low byte) t0cntl 68 44h ? r timer 0 counter (high byte) t0cnth 67 43h ? r timer 0 data register (low byte) t0datal 66 42h ffh r/w timer 0 data register (high byte) t0datah 65 41h ffh r/w timer 0 control register t0con 64 40h 00h r/w location 36h-3fh are not mapped port 7 control register p7con 53 35h 00h r/w port 6 control register p6con 52 34h 00h r/w port 5 control register (low byte) p5conl 51 33h 00h r/w port 5 control register (high byte) p5conh 50 32h 00h r/w port 4 control register (low byte) p4conl 49 31h 00h r/w port 4 control register (high byte) p4conh 48 30h 00h r/w location 2ch-2fh are not mapped port 3 control register (low byte) p3conl 43 2bh 00h r/w port 3 control register (high byte) p3conh 42 2ah 00h r/w port 2 control register (low byte) p2conl 41 29h 00h r/w port 2 control register (high byte) p2conh 40 28h 00h r/w locations 23h-27h are not mapped port 1 pull-up control register p1pur 34 22h 00h r/w port 1 control register p1con 33 21h 00h r/w port 0 control register p0con 32 20h 00h r/w
memory map S3CK225 /fk225 4- 4 table 4-1. registers (continued) register name mnemonic decimal hex reset r/w locations 78h-7fh are not mapped op amp control register opcon 119 77h 00h r/w d/a converter data register (low byte) dadatal 118 76h 00h r/w d/a converter data register (high byte) dadatah 117 75h 00h r/w d/a converter control register dacon 116 74h 00h r/w locations 73h is not mapped main system clock output control register clocon 114 72h 00h r/w locations 71h is not mapped watch timer control register wtcon 112 70h 00h r/w location 64h-6fh are not mapped lcd port control register 2 lpot2 99 63h 00h r/w lcd port control register 1 lpot1 98 62h 00h r/w lcd mode register lmod 97 61h 00h r/w lcd control register lcon 96 60h 00h r/w location 5fh is not mapped a/d converter data register (low byte) addatal 94 5eh ? r a/d converter data register (high byte) addatah 93 5dh ? r a/d converter control register adcon 92 5ch 00h r/w locations 5bh is not mapped serial i/o data register siodata 90 5ah 00h r/w serial i/o pre-scaler register siops 89 59h 00h r/w serial i/o control register siocon 88 58h 00h r/w timer 3 counter t3cnt 87 57h ? r timer 3 data register (low byte) t3datal 86 56h ffh r/w timer 3 data register (high byte) t3datah 85 55h ffh r/w timer 3 control register t3con 84 54h 00h r/w locations 53h is not mapped
S3CK225/fk225 hardw are stack 5- 1 5 hardware stack overview the hardware stack in calmrisc has two usages: ? to save and restore the return pc[19:0] on lcall, calls, ret, and iret instructions. ? temporary storage space for registers on push and pop instructions. when pc[19:0] is saved into or restored from the hardware stack, the access should be 20 bits wide. on the other hand, when a register is pushed into or popped from the hardware stack, the access should be 8 bits wide. hence, to maximize the efficiency of the stack usage, the hardware stack is divided into 3 parts: the extended stack bank (xstack, 4-bits wide), the odd bank (8-bits wide), and the even bank (8-bits wide). 3 0 7 0 7 0 level 0 level 1 level 2 level 14 level 15 xstack odd bank even bank hardware stack 0 1 5 stack pointer sptr [5:0] odd or even bank selector stack level pointer figure 5-1. hardware stack
hardware stack s3ck 225/fk225 5- 2 the top of the stack (tos) is pointed to by a stack pointer, called sptr[5:0] . the upper 5 bits of the stack pointer, sptr[5:1], points to the stack level into which either pc[19:0] or a register is saved. for example, if sptr[5:1] is 5h or tos is 5, then level 5 of xstack is empty and either level 5 of the odd bank or level 5 of the even bank is empty. in fact, sptr[0], the stack bank selection bit, indicates which bank(s) is empty. if sptr[0] = 0, both level 5 of the even and the odd banks are empty. on the other hand, if sptr[0] = 1, level 5 of the odd bank is empty, but level 5 of the even bank is occupied. this situation is well illustrated in the figure below. level 0 level 1 level 2 level 15 xstack odd bank even bank 0 1 5 sptr [5:0] bank selector stack level pointer level 3 level 4 level 5 0 0 1 1 0 0 level 0 level 1 level 2 level 15 xstack odd bank even bank 0 1 5 sptr [5:0] bank selector stack level pointer level 3 level 4 level 5 0 0 1 1 1 0 figure 5-2. even and odd bank selection example as can be seen in the above example, sptr[5:1] is used as the hardware stack pointer when pc[19:0] is pushed or popped and sptr[5:0] as the hardware stack pointer when a register is pushed or popped. note that xstack is used only for storing and retrieving pc[19:16]. let us consider the cases where pc[19:0] is pushed into the hardware stack (by executing lcall/calls instructions or by interrupts/exceptions being served) or is retrieved from the hardware stack (by executing ret/iret instructions). regardless of the stack bank selection bit ( sptr[0]), tos of the even bank and the odd bank store or return pc[7:0] or pc[15:8], respectively. this is illustrated in the following figures.
S3CK225/fk225 hardw are stack 5- 3 level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector level 5 0 0 1 1 0 0 level 6 0 level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector stack level pointer level 5 0 1 1 0 0 0 level 6 0 pc[7:0] stack level pointer level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector level 5 1 0 1 1 0 0 level 6 0 level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector level 5 1 1 1 0 0 0 level 6 0 by executing ret, iret by executing call, calls or interrupts/exceptions stack level pointer stack level pointer pc[19:16] pc[15:8] pc[15:8] pc[19:16] pc[7:0] by executing ret, iret by executing call, calls or interrupts/exceptions figure 5-3. stack operation with pc [19:0] as can be seen in the figures, when stack operations with pc[19:0] are performed, the stack level pointer sptr[5:1] ( not sptr[5:0]) is either incremented by 1 (when pc[19:0] is pushed into the stack) or decremented by 1 (when pc[19:0] is popped from the stack). the stack bank selection bit ( sptr[0]) is unchanged. if a calmrisc core input signal np64kw is 0, which signifies that only pc[15:0] is meaningful, then any access to xstack is totally deactivated from the stack operations with pc. therefore, xstack has no meaning when the input pin signal, np64kw , is tied to 0. in that case, xstack doesn ? t have to even exist. as a matter of fact, xstack is not included in calmrisc core itself and it is interfaced through some specially reserved core pin signals ( npush, nstack , xhsi[3:0] , xsho[3:0] ), if the program address space is more than 64 k words (see the core pin signal section for details). with regards to stack operations with registers, a similar argument can be made. the only difference is that the data written into or read from the stack are a byte. hence, the even bank and the odd bank are accessed alternately as shown below.
hardware stack s3ck 225/fk225 5- 4 level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector level 5 0 0 1 1 0 0 level 6 0 level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector stack level pointer level 5 1 0 1 1 0 0 level 6 0 register stack level pointer level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector level 5 1 0 1 1 0 0 level 6 0 level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector level 5 0 1 1 0 0 0 level 6 0 register pop register push register stack level pointer stack level pointer pop register push register figure 5-4. stack operation with registers when the bank selection bit ( sptr[0]) is 0, then the register is pushed into the even bank and the bank selection bit is set to 1. in this case, the stack level pointer is unchanged. when the bank selection bit ( sptr[0]) is 1, then the register is pushed into the odd bank, the bank selection bit is set to 0, and the stack level pointer is incremented by 1. unlike the push operations of pc[19:0], any data are not written into xstack in the register push operations. this is illustrated in the example figures. when a register is pushed into the stack, sptr[5:0] is incremented by 1 ( not the stack level pointer sptr[5:1]). the register pop operations are the reverse processes of the register push operations. when a register is popped out of the stack, sptr[5:0] is decremented by 1 ( not the stack level pointer sptr[5:1]). hardware stack overflow/underflow happens when the msb of the stack level pointer, sptr[5], is 1. this is obvious from the fact that the hardware stack has only 16 levels and the following relationship holds for the stack level pointer in a normal case. suppose the stack level pointer sptr[5:1] = 15 (or 01111b in binary format) and the bank selection bit sptr[0] = 1. here if either pc[19:0] or a register is pushed, the stack level pointer is incremented by 1. therefore, sptr[5:1] = 16 (or 10000b in binary format) and sptr[5] = 1, which implies that the stack is overflowed. the situation is depicted in the following.
S3CK225/fk225 hardw are stack 5- 5 level 0 level 15 xstack odd bank even bank push register 1 1 1 1 1 0 1 5 sptr [5:0] 0 level 1 level 14 level 0 level 15 xstack odd bank even bank 0 0 0 0 0 1 1 5 sptr [5:0] 0 level 1 level 14 level 0 level 15 1 0 0 0 0 1 1 5 sptr [5:0] 0 level 1 level 14 xstack odd bank even bank push pc [19:0] register pc[19:16] pc[15:8] pc[7:0] figure 5-5. stack overflow
hardware stack s3ck 225/fk225 5- 6 the first overflow happens due to a register push operation. as explained earlier, a register push operation increments sptr[5:0] (not sptr[5:1]) , which results in sptr[5] = 1, sptr[4:1] = 0 and sptr[0] = 0. as indicated by sptr[5] = 1, an overflow happens. note that this overflow doesn ? t overwrite any data in the stack. on the other hand, when pc[19:0] is pushed, sptr[5:1] is incremented by 1 instead of sptr[5:0], and as expected, an overflow results. unlike the first overflow, pc[7:0] is pushed into level 0 of the even bank and the data that has been there before the push operation is overwritten . a similar argument can be made about stack underflows. note that any stack operation, which causes the stack to overflow or underflow, doesn ? t necessarily mean that any data in the stack are lost, as is observed in the first example. in sr1, there is a status flag, sf (stack full flag), which is exactly the same as sptr[5]. in other words, the value of sptr[5] can be checked by reading sf (or sr1[4]). sf is not a sticky flag in the sense that if there was a stack overflow/underflow but any following stack access instructions clear sptr[5] to 0, then sf = 0 and programmers cannot tell whether there was a stack overflow/underflow by reading sf. for example, if a program pushes a register 64 times in a row, sptr[5:0] is exactly the same as sptr[5:0] before the push sequence. therefore, special attention should be paid. another mechanism to detect a stack overflow/underflow is through a stack exception. a stack exception happens only when the execution of any stack access instruction results in sf = 1 (or sptr[5] = 1). suppose a register push operation makes sf = 1 (the sf value before the push operation doesn ? t matter). then the stack exception due to the push operation is immediately generated and served if the stack exception enable flag (exe of sr0) is 1. if the stack exception enable flag is 0, then the generated interrupt is not served but pending. sometime later when the stack exception enable flag is set to 1, the pending exception request is served even if sf = 0. more details are available in the stack exception section.
S3CK225/fk225 excep tions 6- 1 6 exceptions overview exceptions in calmrisc are listed in the table below. exception handling routines, residing at the given addresses in the table, are invoked when the corresponding exception occurs. the start address of each exception routine is specified by concatenation 0h (leading 4 bits of 0) and the 16-bit data in the exception vector listed in the table. for example, the interrupt service routine for irq[0] starts from 0h:pm[00002h]. note that ":"means concatenation and pm[*] stands for the 16-bit content at the address * of the program memory. aside from the exception due to reset release, the current pc is pushed in the stack on an exception. when an exception is executed due to irq[1:0]/iexp, the global interrupt enable flag, ie bit (sr0[1]), is set to 0, whereas ie is set to 1 when iret or an instruction that explicitly sets ie is executed. table 6-1. exceptions name address priority description reset 00000h 1st exception due to reset release. ? 00001h ? reserved irq[0] 00002h 3rd exception due to nirq[0] signal. maskable by setting ie/ie0. irq[1] 00003h 4th exception due to nirq[1] signal. maskable by setting ie/ie1. iexp 00004h 2nd exception due to stack full. maskable by setting exe. ? 00005h ? reserved. ? 00006h ? reserved. ? 00007h ? reserved. note: break mode due to bkreq has a higher priority than all the exceptions above. that is, when bkreq is active, even the exception due to reset release is not executed. hardware reset when hardware reset is active (the reset input signal pin nres = 0), the control pins in the calmrisc core are initialized to be disabled, and sr0 and sptr (the hardware stack pointer) are initialized to be 0. additionally, the interrupt sensing block is cleared. when hardware reset is released ( nres = 1), the reset exception is executed by loading the jp instruction in ir (instruction register) and 0h:0000h in pc. therefore, when hardware reset is released, the "jp {0h:pm[00000h]}" instruction is executed.
exceptions S3CK225 /fk225 6- 2 irq[0] exception when a core input signal nirq[0] is low, sr0[6] (ie0) is high, and sr0[1] ( ie) is high, irq[0] exception is generated, and this will load the call instruction in ir (instruction register) and 0h:0002h in pc. therefore, on an irq[0] exception, the "call {0h:pm[00002h]}" instruction is executed. when the irq[0] exception is executed, sr0[1] ( ie) is set to 0. irq[1] exception (level-sensitive) when a core input signal nirq[1] is low, sr0[7] (ie1) is high, and sr0[1] ( ie) is high, irq[1] exception is generated, and this will load the call instruction in ir (instruction register) and 0h:0003h in pc. therefore, on an irq[1] exception, the "call {0h:pm[00003h]}" instruction is executed. when the irq[1] exception is executed, sr0[1] ( ie) is set to 0. hardware stack full exception a stack full exception occurs when a stack operation is performed and as a result of the stack operation sptr[5] (sf) is set to 1. if the stack exception enable bit, exe (sr0[5]), is 1, the stack full exception is served. one exception to this rule is when nnmi causes a stack operation that sets sptr[5] (sf), since it has higher priority. handling a stack full exception may cause another stack full exception. in this case, the new exception is ignored. on a stack full exception, the call instruction is loaded in ir (instruction register) and 0h:0004h in pc. therefore, when the stack full exception is activated, the "call {0h:pm[00004h]}" instruction is executed. when the exception is executed, sr0[1] ( ie) is set to 0. break exception break exception is reserved only for an in-circuit debugger. when a core input signal, bkreq , is high, the calmrisc core is halted or in the break mode, until bkreq is deactivated. another way to drive the calmrisc core into the break mode is by executing a break instruction, break. when break is fetched, it is decoded in the fetch cycle (if stage) and the calmrisc core output signal nbkack is generated in the second cycle (id/mem stage). an in-circuit debugger generates bkreq active by monitoring nbkack to be active. break instruction is exactly the same as the nop (no operation) instruction except that it does not increase the program counter and activates nbkack in the second cycle (or id/mem stage of the pipeline). there, once break is encountered in the program execution, it falls into a deadlock. break instruction is reserved for in-circuit debuggers only, so it should not be used in user programs.
S3CK225/fk225 excep tions 6- 3 exceptions ( or interrupts) timer 0 match/capture timer 0 overflow int 3 timer 2 overflow timer 3 match sio int ivec0 00002h ivec1 00003h watch timer int 0 int 1 int 2 stack full int 00004h sf_excep - h/w, s/w h/w, s/w h/w, s/w h/w, s/w h/w, s/w h/w, s/w h/w, s/w h/w, s/w h/w notes: 1. reset has the highest priority for an interrupt level, followed by sf_excep, ivec0 and ivec1. 2. in the case of ivec0 and ivec1, one interrupt vector has several interrupt sources. the priority of the sources is controlled by setting the ipr register. 3. external interrupts are triggered by rising or falling edge, depending on the corresponding control register setting. 4. after system reset, the ipr register is in unknown status, so it must be set the ipr register with proper value. 5. the pending bit is cleared by hardware when cpu reads the iir registser value. h/w, s/w vector source level reset (clear) reset reset 00000h - timer 1 match timer 2 match h/w, s/w h/w, s/w h/w, s/w 00001h not used nmi basic timer overflow h/w, s/w figure 6-1. interrupt structure
exceptions S3CK225 /fk225 6- 4 ipr0 logic iir0 cpu ivec0 ipr0 imr0 logic imr0 stop & idle release imr1 logic imr1 ipr1 ipr1 logic ivec1 iir1 irq1.0 irq1.1 irq1.2 irq1.3 irq1.4 irq1.5 irq1.6 irq1.7 note: the irq register value is cleared by h/w when the iir register is read by the programmer in an interrupt service routine. however, if you want to clear by s/w, then write the proper value to the iir register like as in the example above. to clear all the bits of irqx register at one time write "#08h" to the iirx register. clear (when writing clear bit value to bit 2-0) clear (when writing clear bit value to bit 2-0) ld r0, #x5h ld iir0, r0 irq0.5 is cleared ex) ld r0, #x2h ld iir1, r0 irq1.2 is cleared ex) irq0.0 irq0.1 irq0.2 irq0.3 irq0.4 irq0.5 irq0.6 irq0.7 timer 0 overflow timer 0 match/capture timer 1 match timer 2 match timer 3 match timer 2 overflow sio basic timer overflow not used int3 not used not used watch timer int0 int1 int2 figure 6-2. interrupt structure
S3CK225/fk225 excep tions 6- 5 interrupt mask registers .7 .6 .5 .4 .3 .2 .1 .0 interrupt mask register0 (imr0) 05h, r/w, reset: 00h irq0.0 irq0.1 irq0.2 irq0.3 irq0.4 irq0.5 irq0.6 irq0.7 interrupt request enable bits: 0 = disable interrupt request 1 = enable interrupt request note: if you want to change the value of the imr register, then you first make disable global int by di instruction, and change the value of the imr register. .7 .6 .5 .4 .3 .2 .1 .0 interrupt mask register1 (imr1) 09h, r/w, reset: 00h irq1.0 irq1.1 irq1.2 irq1.3 irq1.4 not used not used not used figure 6-3. interrupt mask register
exceptions S3CK225 /fk225 6- 6 interrupt priority register group a 0 = irqx.0 > irqx.1 1 = irqx.1 > irqx.0 interrupt priority registers (ipr0:06h,ipr1:0ah, r/w ) ipr group a note: if you want to change the value of the ipr register, then you first make disable global int by di instruction, and change the value of the ipr register. after reset, ipr register is unknown status, so user must set the ipr register with proper value. ipr group b ipr group c irqx.0 irqx.1 irqx.2 irqx.3 irqx.4 irqx.5 irqx.6 irqx.7 group b 0 = irqx.2 > (irqx.3, irqx.4) 1 = (irqx.3,irqx.4) > irqx.2 subgroup b 0 = irqx.3 > irqx.4 1 = irqx.4 > irqx.3 group c 0 = irqx.5 > (irqx.6, irqx.7) 1 = (irqx.6, irqx.7) > irqx.5 subgroup c 0 = irqx.6 > irqx.7 1 = irqx.7 > irqx.6 .7 .6 .5 .4 .3 .2 .1 .0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 not used b>c>a a>b>c b>a>c c>a>b c>b>a a>c>b not used .7 .4 .1 group priority: figure 6-4. interrupt priority register
S3CK225/fk225 excep tions 6- 7 + + programming tip ? interrupt programming tip 1 jumped from vector 2 push sr1 push r0 ld r0, iir00 cp r0, #03h jr ule, lte03 cp r0, #05h jr ule, lte05 cp r0, #06h jp eq, irq6_srv jp t, irq7_srv lte05 cp r0, #04 jp eq, irq4_srv jp t, irq5_srv lte03 cp r0, #01 jr ule, lte01 cp r0, #02 jp eq, irq2_srv jp t, irq3_srv lte01 cp r0, #00h jp eq, irq0_srv jp t, irq1_srv irq0_srv ; ? service for irq0 pop r0 pop sr1 iret irq1_srv ; ? service for irq1 pop r0 pop sr1 iret irq7_srv ; ? service for irq7 pop r0 pop sr1 iret note if the sr0 register is changed in the interrupt service routine, then the sr0 register must be pushed and popped in the interrupt service routine.
exceptions S3CK225 /fk225 6- 8 + + programming tip ? interrupt programming tip 2 jumped from vector 2 push sr1 push r0 push r1 ld r0, iir00 sl r0 ld r1, # < tbl_intx add r0, # > tbl_intx ld ilh, r1 ld ill, r0 lret tbl_intx ljp irq0_svr ljp irq1_svr ljp irq2_svr ljp irq3_svr ljp irq4_svr ljp irq5_svr ljp irq6_svr ljp irq7_svr irq0_srv ; ? service for irq0 pop r1 pop r0 pop sr1 iret irq1_srv ; ? service for irq1 pop r1 pop r0 pop sr1 iret irq7_srv ; ? service for irq7 pop r1 pop r0 pop sr1 iret note 1. if the sr0 register is changed in the interrupt service routine, then the sr0 register must be pushed and popped in the interrupt service routine. 2. above example is assumed that rom size is less than 64k-word and all the ljp instructions in the jump table ( tbl_intx) is in the same page.
S3CK225/fk225 instr uction set 7- 1 7 instruction set overview glossary this chapter describes the calmrisc instruction set and the details of each instruction are listed in alphabetical order. the following notations are used for the description. table 7-1. instruction notation conventions notation interpretation < opn> operand n. n can be omitted if there is only one operand. typically, is the destination (and source) operand and is a source operand. gpr general purpose register spr special purpose register (idl0, idl1, idh, sr0, ilx, ilh, ill, sr1) adr:n n-bit address specifier @ idm content of memory location pointed by id0 or id1 ( adr:n) content of memory location specified by adr:n cc:4 4-bit condition code. table 7-6 describes cc:4. imm:n n-bit immediate number & bit-wise and | bit-wise or ~ bit-wise not ^ bit-wise xor n**m mth power of n (n) m m-based number n as additional note, only the affected flags are described in the tables in this section. that is, if a flag is not affected by an operation, it is not specified.
instruction set s3c k225/fk225 7- 2 instruction set map table 7-2.overall instruction set map ir [12:10]000 001 010 011 100 101 110 111 [15:13,7:2] 000 xxxxxx add gpr, #imm:8 sub gpr, #imm:8 cp gpr, #imm8 ld gpr, #imm:8 tm gpr, #imm:8 and gpr, #imm:8 or gpr, #imm:8 xor gpr, #imm:8 001 xxxxxx add gpr, @ idm sub gpr, @ idm cp gpr, @ idm ld gpr, @ idm ld @ idm, gpr and gpr, @ idm or gpr, @ idm xor gpr, @ idm 010 xxxxxx add gpr, adr:8 sub gpr, adr:8 cp gpr, adr:8 ld gpr, adr:8 bitt adr:8.bs bits adr:8.bs 011 xxxxxx adc gpr, adr:8 sbc gpr, adr:8 cpc gpr, adr:8 ld adr:8, gpr bitr adr:8.bs bitc adr:8.bs 100 000000 add gpr, gpr sub gpr, gpr cp gpr, gpr bms/bm c ld spr0, #imm:8 and gpr, adr:8 or gpr, adr:8 xor gpr, adr:8 100 000001 adc gpr, gpr sbc gpr, gpr cpc gpr, gpr invalid 100 000010 invalid invalid invalid invalid 100 000011 and gpr, gpr or gpr, gpr xor gpr, gpr invalid 100 00010x sla/sl/ rlc/rl/ sra/sr/ rrc/rr/ gpr inc/incc /dec/ decc/ com/ com2/ comc gpr invalid invalid 100 00011x ld spr, gpr ld gpr, spr swap gpr, spr ld tbh/tbl, gpr 100 00100x push spr pop spr invalid invalid 100 001010 push gpr pop gpr ld gpr, gpr ld gpr, tbh/tbl
S3CK225/fk225 instr uction set 7- 3 table 7-2. overall instruction set map (continued) ir [12:10]000 001 010 011 100 101 110 111 100 001011 pop invalid ldc invalid ld spr0, #imm:8 and gpr, adr:8 or gpr, adr:8 xor gpr, adr:8 100 00110x ret/lret/ iret/nop/ break invalid invalid invalid 100 00111x invalid invalid invalid invalid 100 01xxxx ld gpr:bank, gpr:bank and sr0, #imm:8 or sr0, #imm:8 bank #imm:2 100 100000 100 110011 invalid invalid invalid invalid 100 1101xx lcall cc:4, imm:20 (2-word instruction) 100 1110xx llnk cc:4, imm:20 (2-word instruction) 100 1111xx ljp cc:4, imm:20 (2-word instruction) [15:10] 101 xxx jr cc:4, imm:9 110 0xx calls imm:12 110 1xx lnks imm:12 111 xxx cld gpr, imm:8 / cld imm:8, gpr / jnzd gpr, imm:8 / sys #imm:8 / cop #imm:12 note: ? invalid ? - invalid instruction.
instruction set s3c k225/fk225 7- 4 table 7-3. instruction encoding instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 add gpr, #imm:8 000 000 gpr imm[7:0] sub gpr, #imm:8 001 cp gpr, #imm:8 010 ld gpr, #imm:8 011 tm gpr, #imm:8 100 and gpr, #imm:8 101 or gpr, #imm:8 110 xor gpr, #imm:8 111 add gpr, @ idm 001 000 gpr idx mod offset[4:0] sub gpr, @ idm 001 cp gpr, @ idm 010 ld gpr, @ idm 011 ld @ idm, gpr 100 and gpr, @ idm 101 or gpr, @ idm 110 xor gpr, @ idm 111 add gpr, adr:8 010 000 gpr adr[7:0] sub gpr, adr:8 001 cp gpr, adr:8 010 ld gpr, adr:8 011 bitt adr:8.bs 10 bs bits adr:8.bs 11 adc gpr, adr:8 011 000 gpr adr[7:0] sbc gpr, adr:8 001 cpc gpr, adr:8 010 ld adr:8, gpr 011 bitr adr:8.bs 10 bs bitc adr:8.bs 11
S3CK225/fk225 instr uction set 7- 5 table 7-3. instruction encoding (continued ) instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 add gprd, gprs 100 000 gprd 000000 gprs sub gprd, gprs 001 cp gprd, gprs 010 bms/bmc 011 adc gprd, gprs 000 000001 sbc gprd, gprs 001 cpc gprd, gprs 010 invalid 011 invalid ddd 000010 and gprd, gprs 000 000011 or gprd, gprs 001 xor gprd, gprs 010 invalid 011 aluop1 000 gpr 00010 aluop1 aluop2 001 gpr aluop2 invalid 010?011 xx xxx ld spr, gpr 000 gpr 00011 spr ld gpr, spr 001 gpr spr swap gpr, spr 010 gpr spr ld tbl, gpr 011 gpr x 0 x ld tbh, gpr x 1 x push spr 000 xx 00100 spr pop spr 001 xx spr invalid 010?011 xx xxx push gpr 000 gpr 001010 gpr pop gpr 001 gpr gpr ld gprd, gprs 010 gprd gprs ld gpr, tbl 011 gpr 0 x ld gpr, tbh 1 x pop 000 xx 001011 xx ldc @il 010 0 x ldc @il+ 1 x invalid 001, 011 xx note: "x" means not applicable. table 7-3. instruction encoding (concluded )
instruction set s3c k225/fk225 7- 6 instruction 15-13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 nd word modop1 100 000 xx 00110 modop1 ? invalid 001?011 xx xxx invalid 000 xx 01 xxxxxx and sr0, #imm:8 001 imm[7:6] imm[5:0] or sr0, #imm:8 010 imm[7:6] bank #imm:2 011 xx x imm [1:0] xxx invalid 0 xxxx 10000000-11001111 lcall cc, imm:20 cc 1101 imm[19:16] imm[15:0] llnk cc, imm:20 1110 ljp cc, imm:20 1111 ld spr0, #imm:8 1 00 spr0 imm[7:0] ? and gpr, adr:8 01 gpr adr[7:0] or gpr, adr:8 10 xor gpr, adr:8 11 jr cc, imm:9 101 imm [8] cc imm[7:0] calls imm:12 110 0 imm[11:0] lnks imm:12 1 cld gpr, imm:8 111 0 00 gpr imm[7:0] cld imm:8, gpr 01 gpr jnzd gpr, imm:8 10 gpr sys #imm:8 11 xx cop #imm:12 1 imm[11:0] notes: 1. "x" means not applicable. 2. there are several modop1 codes that can be used, as described in table 7-9. 3. the operand 1(gpr) of the instruction jnzd is bank 3?s register.
S3CK225/fk225 instr uction set 7- 7 table 7-4. index code information (? idx?) symbol code description id0 0 index 0 idh:idl0 id1 1 index 1 idh:idl1 table 7-5. index modification code information (?mod?) symbol code function @ idx + offset:5 00 dm[ idx], idx ? idx + offset @[ idx - offset:5] 01 dm[ idx + (2?s complement of offset:5)], idx ? idx + (2?s complement of offset:5) @[ idx + offset:5]! 10 dm[ idx + offset], idx ? idx @[ idx - offset:5]! 11 dm[ idx + (2?s complement of offset:5)], idx ? idx note: carry from idl is propagated to idh. in case of @[ idx - offset:5] or @[ idx - offset:5]!, the assembler should convert offset:5 to the 2?s complement format to fill the operand field (offset[4:0]). furthermore, @[ idx - 0] and @[ idx - 0]! are converted to @[ idx + 0] and @[ idx + 0]!, respectively. table 7-6. condition code information (?cc?) symbol (cc:4) code function blank 0000 always nc or ult 0001 c = 0, unsigned less than c or uge 0010 c = 1, unsigned greater than or equal to z or eq 0011 z = 1, equal to nz or ne 0100 z = 0, not equal to ov 0101 v = 1, overflow - signed value ule 0110 ~c | z, unsigned less than or equal to ugt 0111 c & ~z, unsigned greater than zp 1000 n = 0, signed zero or positive mi 1001 n = 1, signed negative pl 1010 ~n & ~z, signed positive zn 1011 z | n, signed zero or negative sf 1100 stack full ec0-ec2 1101-1111 ec[0] = 1/ec[1] = 1/ec[2] = 1 note: ec[2:0] is an external input ( calmrisc core?s point of view) and used as a condition.
instruction set s3c k225/fk225 7- 8 table 7-7. ?aluop1? code information symbol code function sla 000 arithmetic shift left sl 001 shift left rlc 010 rotate left with carry rl 011 rotate left sra 100 arithmetic shift right sr 101 shift right rrc 110 rotate right with carry rr 111 rotate right table 7-8. ?aluop2? code information symbol code function inc 000 increment incc 001 increment with carry dec 010 decrement decc 011 decrement with carry com 100 1?s complement com2 101 2?s complement comc 110 1?s complement with carry ? 111 reserved table 7-9. ?modop1? code information symbol code function lret 000 return by il ret 001 return by hs iret 010 return from interrupt (by hs) nop 011 no operation break 100 reserved for debugger use only ? 101 reserved ? 110 reserved ? 111 reserved
S3CK225/fk225 instr uction set 7- 9 quick reference operation op1 op2 function flag # of word / cycle and or xor add sub cp gpr adr:8 #imm:8 gpr @ idm op1 ? op1 & op2 op1 ? op1 | op2 op1 ? op1 ^ op2 op1 ? op1 + op2 op1 ? op1 + ~op2 + 1 op1 + ~op2 + 1 z,n z,n z,n c,z,v,n c,z,v,n c,z,v,n 1w1c adc sbc cpc gpr gpr adr:8 op1 ? op1 + op2 + c op1 ? op1 + ~op2 + c op1 + ~op2 + c c,z,v,n c,z,v,n c,z,v,n tm gpr #imm:8 op1 & op2 z,n bits bitr bitc r3 adr:8.bs op1 ? (op2[bit] ? 1) op1 ? (op2[bit] ? 0) op1 ? ~(op2[bit]) z z z 1w2c bitt z ? ~(op2[bit]) z 1w1c bms/bmc ? ? tf ? 1 / 0 ? push pop gpr ? hs[ sptr] ? gpr, ( sptr ? sptr + 1) gpr ? hs[ sptr - 1], ( sptr ? sptr - 1) ? z,n push pop spr ? hs[ sptr] ? spr, ( sptr ? sptr + 1) spr ? hs[ sptr - 1], ( sptr ? sptr - 1) ? pop ? ? sptr ? sptr ? 2 ? sla sl rlc rl sra sr rrc rr inc incc dec decc com com2 comc gpr ? c ? op1[7], op1 ? {op1[6:0], 0} c ? op1[7], op1 ? {op1[6:0], 0} c ? op1[7], op1 ? {op1[6:0], c} c ? op[7], op1 ? {op1[6:0], op1[7]} c ? op[0], op1 ? {op1[7],op1[7:1]} c ? op1[0], op1 ? {0, op1[7:1]} c ? op1[0], op1 ? {c, op1[7:1]} c ? op1[0], op1 ? {op1[0], op1[7:1]} op1 ? op1 + 1 op1 ? op1 + c op1 ? op1 + 0ffh op1 ? op1 + 0ffh + c op1 ? ~op1 op1 ? ~op1 + 1 op1 ? ~op1 + c c,z,v,n c,z,n c,z,n c,z,n c,z,n c,z,n c,z,n c,z,n c,z,v,n c,z,v,n c,z,v,n c,z,v,n z,n c,z,v,n c,z,v,n
instruction set s3c k225/fk225 7- 10 quick reference ( continued ) operation op1 op2 function flag # of word / cycle ld gpr :bank gpr :bank op1 ? op2 z,n 1w1c ld spr0 #imm:8 op1 ? op2 ? ld gpr gpr spr adr:8 @ idm #imm:8 tbh/tbl op1 ? op2 z,n ld spr tbh/tbl gpr op1 ? op2 ? ld adr:8 gpr op1 ? op2 ? ld @ idm gpr op1 ? op2 ? ldc @il @il+ ? (tbh:tbl) ? pm[(ilx:ilh:ill)], ill++ if @il+ ? 1w2c and or sr0 #imm:8 sr0 ? sr0 & op2 sr0 ? sr0 | op2 ? 1w1c bank #imm:2 ? sr0[4:3] ? op2 ? swap gpr spr op1 ? op2, op2 ? op1 (excluding sr0/sr1) ? lcall cc imm:20 ? if branch taken, push xstack, hs[15:0] ? {pc[15:12],pc[11:0] + 2} and pc ? op1 else pc[11:0] ? pc[11:0] + 2 ? 2w2c llnk cc imm:20 ? if branch taken, il[19:0] ? {pc[19:12], pc[11:0] + 2} and pc ? op1 else pc[11:0] ? pc[11:0] + 2 ? calls imm:12 ? push xstack, hs[15:0] ? {pc[15:12], pc[11:0] + 1} and pc[11:0] ? op1 ? 1w2c lnks imm:12 ? il[19:0] ? {pc[19:12], pc[11:0] + 1} and pc[11:0] ? op1 ? jnzd rn imm:8 if ( rn == 0) pc ? pc[delay slot] - 2?s complement of imm:8, rn-- else pc ? pc[delay slot]++, rn-- ? ljp cc imm:20 ? if branch taken, pc ? op1 else pc[11:0] < pc[11:0] + 2 ? 2w2c jr cc imm:9 ? if branch taken, pc[11:0] ? pc[11:0] + op1 else pc[11:0] ? pc[11:0] + 1 ? 1w2c note: op1 - operand1, op2 - operand2, 1w1c - 1-word 1-cycle instruction, 1w2c - 1-word 2-cycle instruction, 2w2c - 2-word 2-cycle instruction. the rn of instruction jnzd is bank 3?s gpr.
S3CK225/fk225 instr uction set 7- 11 quick reference ( concluded ) operation op1 op2 function flag # of word / cycle lret ret iret nop break ? ? pc ? il[19:0] pc ? hs[ sptr - 2], ( sptr ? sptr - 2) pc ? hs[ sptr - 2], ( sptr ? sptr - 2) no operation no operation and hold pc ? 1w2c 1w2c 1w2c 1w1c 1w1c sys #imm:8 ? no operation but generates syscp[7:0] and nsysid ? 1w1c cld imm:8 gpr op1 ? op2, generates syscp[7:0], ncldid, and cldwr ? cld gpr imm:8 op1 ? op2, generates syscp[7:0], ncldid, and cldwr z,n cop #imm:12 ? generates syscp[11:0] and ncopid ? notes: 1. op1 - operand1, op2 - operand2, sptr - stack pointer register, 1w1c - 1-word 1-cycle instruction, 1w2c - 1-word 2-cycle instruction 2. pseudo instructions ? scf/rcf carry flag set or reset instruction ? stop/idle mcu power saving instructions ? ei/di exception enable and disable instructions ? jp/lnk/call if jr/lnks/calls commands (1 word instructions) can access the target address, there is no conditional code in the case of call/lnk, and the jp/lnk/call commands are assembled to jr/lnks/calls in linking time, or else the jp/lnk/call commands are assembled to ljp/llnk/lcall (2 word instructions) instructions.
instruction set s3c k225/fk225 7- 12 instruction group summary alu instructions ?alu instructions? refer to the operations that use alu to generate results. alu instructions update the values in status register 1 (sr1), namely carry (c), zero (z), overflow (v), and negative (n), depending on the operation type and the result. aluop gpr, adr:8 performs an alu operation on the value in gpr and the value in dm[adr:8] and stores the result into gpr. aluop = add, sub, cp, and, or, xor for sub and cp, gpr+(not dm[adr:8])+1 is performed. adr:8 is the offset in a specific data memory page. the data memory page is 0 or the value of idh (index of data memory higher byte register), depending on the value of eid in status register 0 (sr0). operation gpr ? gpr aluop dm[00h:adr:8] if eid = 0 gpr ? gpr aluop dm[idh:adr8] if eid = 1 note that this is an 7-bit operation. example add r0, 80h // assume eid = 1 and idh = 01h // r0 ? r0 + dm[0180h] aluop gpr, #imm:8 stores the result of an alu operation on gpr and an 7-bit immediate value into gpr. aluop = add, sub, cp, and, or, xor for sub and cp, gpr+(not #imm:8)+1 is performed. #imm:8 is an 7-bit immediate value. operation gpr ? gpr aluop #imm:8 example add r0, #7ah // r0 ? r0 + 7ah
S3CK225/fk225 instr uction set 7- 13 aluop gprd, gprs store the result of aluop on gprs and gprd into gprd. aluop = add, sub, cp, and, or, xor for sub and cp, gprd + (not gprs) + 1 is performed. gprs and gprd need not be distinct. operation gprd ? gprd aluop gprs gprd - gprs when aluop = cp (comparison only) example add r0, r1 // r0 ? r0 + r1 aluop gpr, @ idm performs aluop on the value in gpr and dm[id] and stores the result into gpr. index register id is idh:idl (idh:idl0 or idh:idl1). aluop = add, sub, cp, and, or, xor for sub and cp, gpr+(not dm[ idm])+1 is performed. idm = idx+off:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! ( idx = id0 or id1) operation gpr - dm[ idm] when aluop = cp (comparison only) gpr ? gpr aluop dm[ idx], idx ? idx + offset:5 when idm = idx + offset:5 gpr ? gpr aluop dm[ idx - offset:5], idx ? idx - offset:5 when idm = [ idx - offset:5] gpr ? gpr aluop dm[ idx + offset:5] when idm = [ idx + offset:5]! gpr ? gpr aluop dm[ idx - offset:5] when idm = [ idx - offset:5]! when carry is generated from idl (on a post-increment or pre-decrement), it is propagated to idh. example add r0, @id0+2 // assume id0 = 02ffh // r0 ? r0 + dm[02ffh], idh ? 03h and idl0 ? 01h add r0, @[id0-2] // assume id0 = 0201h // r0 ? r0 + dm[01ffh], idh ? 01h and idl0 ? ffh add r0, @[id1+2]! // assume id1 = 02ffh // r0 ? r0 + dm[0301], idh ? 02h and idl1 ? ffh add r0, @[id1-2]! // assume id1 = 0200h // r0 ? r0 + dm[01feh], idh ? 02h and idl1 ? 00h
instruction set s3c k225/fk225 7- 14 aluopc gprd, gprs performs aluop with carry on gprd and gprs and stores the result into gprd. aluopc = adc, sbc, cpc gprd and gprs need not be distinct. operation gprd ? gprd + gprs + c when aluopc = adc gprd ? gprd + (not gprs) + c when aluopc = sbc gprd + (not gprs) + c when aluopc = cpc (comparison only) example add r0, r2 // assume r1:r0 and r3:r2 are 16-bit signed or unsigned numbers. adc r1, r3 // to add two 16-bit numbers, use add and adc. sub r0, r2 // assume r1:r0 and r3:r2 are 16-bit signed or unsigned numbers. sbc r1, r3 // to subtract two 16-bit numbers, use sub and sbc. cp r0, r2 // assume both r1:r0 and r3:r2 are 16-bit unsigned numbers. cpc r1, r3 // to compare two 16-bit unsigned numbers, use cp and cpc. aluopc gpr, adr:8 performs aluop with carry on gpr and dm[adr:8]. operation gpr ? gpr + dm[adr:8] + c when aluopc = adc gpr ? gpr + (not dm[adr:8]) + c when aluopc = sbc gpr + (not dm[adr:8]) + c when aluopc = cpc (comparison only) cplop gpr (complement operations ) cplop = com, com2, comc operation com gpr not gpr (logical complement) com2 gpr not gpr + 1 (2?s complement of gpr) comc gpr not gpr + c (logical complement of gpr with carry) example com2 r0 // assume r1:r0 is a 16-bit signed number. comc r1 // com2 and comc can be used to get the 2?s complement of it.
S3CK225/fk225 instr uction set 7- 15 incdec gpr (increment/decrement operations) incdec = inc, incc, dec, decc operation inc gpr increase gpr, i.e., gpr ? gpr + 1 incc gpr increase gpr if carry = 1, i.e., gpr ? gpr + c dec gpr decrease gpr, i.e., gpr ? gpr + ffh decc gpr decrease gpr if carry = 0, i.e., gpr ? gpr + ffh + c example inc r0 // assume r1:r0 is a 16-bit number incc r1 // to increase r1:r0, use inc and incc. dec r0 // assume r1:r0 is a 16-bit number decc r1 // to decrease r1:r0, use dec and decc.
instruction set s3c k225/fk225 7- 16 shift/rotate instructions shift (rotate) instructions shift (rotate) the given operand by 1 bit. depending on the operation performed, a number of status register 1 (sr1) bits, namely carry (c), zero (z), overflow (v), and negative (n), are set. sl gpr operation c 7 0 0 gpr carry (c) is the msb of gpr before shifting, negative (n) is the msb of gpr after shifting. overflow (v) is not affected. zero (z) will be 1 if the result is 0. sla gpr operation c 7 0 0 gpr carry (c) is the msb of gpr before shifting, negative (n) is the msb of gpr after shifting. overflow (v) will be 1 if the msb of the result is different from c. z will be 1 if the result is 0. rl gpr operation c 7 0 gpr carry (c) is the msb of gpr before rotating. negative (n) is the msb of gpr after rotatin/g. overflow (v) is not affected. zero (z) will be 1 if the result is 0. rlc gpr operation c 7 0 gpr carry (c) is the msb of gpr before rotating, negative (n) is the msb of gpr after rotating. overflow (v) is not affected. zero (z) will be 1 if the result is 0.
S3CK225/fk225 instr uction set 7- 17 sr gpr operation c 7 0 0 gpr carry (c) is the lsb of gpr before shifting, negative (n) is the msb of gpr after shifting. overflow (v) is not affected. zero (z) will be 1 if the result is 0. sra gpr operation c 7 0 gpr carry (c) is the lsb of gpr before shifting, negative (n) is the msb of gpr after shifting. overflow (v) is not affected. z will be 1 if the result is 0. rr gpr operation c 7 0 gpr carry (c) is the lsb of gpr before rotating. negative (n) is the msb of gpr after rotating. overflow (v) is not affected. zero (z) will be 1 if the result is 0. rrc gpr operation c 7 0 gpr carry (c) is the lsb of gpr before rotating, negative (n) is the msb of gpr after rotating. overflow (v) is not affected. zero (z) will be 1 if the result is 0.
instruction set s3c k225/fk225 7- 18 load instructions load instructions transfer data from data memory to a register or from a register to data memory, or assigns an immediate value into a register. as a side effect, a load instruction placing a value into a register sets the zero (z) and negative (n) bits in status register 1 (sr1), if the placed data is 00h and the msb of the data is 1, respectively. ld gpr, adr:8 loads the value of dm[adr:8] into gpr. adr:8 is offset in the page specified by the value of eid in status register 0 (sr0). operation gpr ? dm[00h:adr:8] if eid = 0 gpr ? dm[idh:adr:8] if eid = 1 note that this is an 7-bit operation. example ld r0, 80h // assume eid = 1 and idh= 01h // r0 ? dm[0180h] ld gpr, @ idm loads a value from the data memory location specified by @ idm into gpr. idm = idx+off:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! ( idx = id0 or id1) operation gpr ? dm[ idx], idx ? idx + offset:5 when idm = idx + offset:5 gpr ? dm[ idx - offset:5], idx ? idx - offset:5 when idm = [ idx - offset:5] gpr ? dm[ idx + offset:5] when idm = [ idx + offset:5]! gpr ? dm[ idx - offset:5] when idm = [ idx - offset:5]! when carry is generated from idl (on a post-increment or pre-decrement), it is propagated to idh. example ld r0, @[id0 + 03h]! // assume idh:idl0 = 0270h // r0 ? dm[0273h], idh:idl0 ? 0270h
S3CK225/fk225 instr uction set 7- 19 ld reg, #imm:8 loads an 7-bit immediate value into reg. reg can be either gpr or an spr0 group register - idh (index of data memory higher byte register), idl0 (index of data memory lower byte register)/ idl1, and status register 0 (sr0). #imm:8 is an 7-bit immediate value. operation reg ? #imm:8 example ld r0 #7ah // r0 ? 7ah ld idh, #03h // idh ? 03h ld gpr:bs:2, gpr:bs:2 loads a value of a register from a specified bank into another register in a specified bank. example ld r0:1, r2:3 // r0 in bank 1, r2 in bank 3 ld gpr, tbh/tbl loads the value of tbh or tbl into gpr. tbh and tbl are 7-bit long registers used exclusively for ldc instructions that access program memory. therefore, after an ldc instruction, ld gpr, tbh/tbl instruction will usually move the data into gprs, to be used for other operations. operation gpr ? tbh (or tbl) example ldc @il // gets a program memory item residing @ ilx:ilh:ill ld r0, tbh ld r1, tbl ld tbh/tbl, gpr loads the value of gpr into tbh or tbl. these instructions are used in pair in interrupt service routines to save and restore the values in tbh/tbl as needed. operation tbh (or tbl) ? gpr ld gpr, spr loads the value of spr into gpr. operation gpr ? spr example ld r0, idh // r0 ? idh
instruction set s3c k225/fk225 7- 20 ld spr, gpr loads the value of gpr into spr. operation spr ? gpr example ld idh, r0 // idh ? r0 ld adr:8, gpr stores the value of gpr into data memory (dm). adr:8 is offset in the page specified by the value of eid in status register 0 (sr0). operation dm[00h:adr:8] ? gpr if eid = 0 dm[idh:adr:8] ? gpr if eid = 1 note that this is an 7-bit operation. example ld 7ah, r0 // assume eid = 1 and idh = 02h. // dm[027ah] ? r0 ld @ idm, gpr loads a value into the data memory location specified by @ idm from gpr. idm = idx+off:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! ( idx = id0 or id1) operation dm[ idx] ? gpr, idx ? idx + offset:5 when idm = idx + offset:5 dm[ idx - offset:5] ? gpr, idx ? idx - offset:5 when idm = [ idx - offset:5] dm[ idx + offset:5] ? gpr when idm = [ idx + offset:5]! dm[ idx - offset:5] ? gpr when idm = [ idx - offset:5]! when carry is generated from idl (on a post-increment or pre-decrement), it is propagated to idh. example ld @[id0 + 03h]!, r0 // assume idh:idl0 = 0170h // dm[0173h] ? r0, idh:idl0 ? 0170h
S3CK225/fk225 instr uction set 7- 21 branch instructions branch instructions can be categorized into jump instruction, link instruction, and call instruction. a jump instruction does not save the current pc, whereas a call instruction saves (?pushes?) the current pc onto the stack and a link instruction saves the pc in the link register il. status registers are not affected. each instruction type has a 2-word format that supports a 20-bit long jump. jr cc:4, imm:9 imm:9 is a signed number (2?s complement), an offset to be added to the current pc to compute the target (pc[19:12]:(pc[11:0] + imm:9)). operation pc[11:0] ? pc[11:0] + imm:9 if branch taken (i.e., cc:4 resolves to be true) pc[11:0] ? pc[11:0] + 1 otherwise example l18411: // assume c urrent pc = 18411h. jr z, 107h // next pc is 18518 (18411h + 107h) if zero (z) bit is set. ljp cc:4, imm:20 jumps to the program address specified by imm:20. if program size is less than 64k word, pc[19:16] is not affected. operation pc[15:0] ? imm[15:0] if branch taken and program size is less than 64k word pc[19:0] ? imm[19:0] if branch taken and program size is equal to 64k word or more pc [11:0] ? pc[11:0] + 1 otherwise example l18411: // assume current pc = 18411h. ljp z, 10107h // next instruction?s pc is 10107h if zero (z) bit is set jnzd rn, imm:8 jumps to the program address specified by imm:8 if the value of the bank 3 register rn is not zero. jnzd performs only backward jumps, with the value of rn automatically decreased. there is one delay slot following the jnzd instruction that is always executed, regardless of whether jnzd is taken or not. operation if ( rn == 0) pc ? pc[delay slot] (-) 2?s complement of imm:8, rn ? rn - 1 else pc ? pc[delay slot] + 1, rn ? rn - 1.
instruction set s3c k225/fk225 7- 22 example loop_a: // start of loop body jnzd r0, loop_a // jump back to loop_a if r0 is not zero add r1, #2 // delay slot, always executed (you must use one cycle ins truction only) calls imm:12 saves the current pc on the stack (?pushes? pc) and jumps to the program address specified by imm:12. the current page number pc[19:12] is not changed. since this is a 1-word instruction, the return address pushed onto the stack is (pc + 1). if np64kw is low when pc is saved, pc[19:16] is not saved in the stack. operation hs[ sptr][15:0] ? current pc + 1 and sptr ? sptr + 2 (push stack) if np64kw = 0 hs[ sptr][19:0] ? current pc + 1 and sptr ? sptr + 2 (push stack) if np64kw = 1 pc[11:0] ? imm:12 example l18411: // assume current pc = 18411h. calls 107h // call the subroutine at 18107h, with the current pc pushed // onto the stack (hs ? 18412h) if np64kw = 1. lcall cc:4, imm:20 saves the current pc onto the stack (pushes pc) and jumps to the program address specified by imm:20. since this is a 2-word instruction, the return address saved in the stack is (pc + 2). if np64kw, a core input signal is low when pc is saved, 0000111111pc[19:16] is not saved in the stack and pc[19:16] is not set to imm[19:16]. operation hs[ sptr][15:0] ? current pc + 2 and sptr + 2 (push stack) if branch taken and np64kw = 0 hs[ sptr][19:0] ? current pc + 2 and sptr + 2 (push stack) if branch taken and np64kw = 1 pc[15:0] ? imm[15:0] if branch taken and np64kw = 0 pc[19:0] ? imm[19:0] if branch taken and np64kw = 1 pc[11:0] ? pc[11:0] + 2 otherwise example l18411: // assume current pc = 18411h. lcall nz, 10107h // call the subroutine at 10107h with the current pc pushed // onto the stack (hs ? 18413h)
S3CK225/fk225 instr uction set 7- 23 lnks imm:12 saves the current pc in il and jumps to the program address specified by imm:12. the current page number pc[19:12] is not changed. since this is a 1-word instruction, the return address saved in il is (pc + 1). if the program size is less than 64k word when pc is saved, pc[19:16] is not saved in ilx. operation il[15:0] ? current pc + 1 if program size is less than 64k word il[19:0] ? current pc + 1 if program size is equal to 64k word or more pc[11:0] ? imm:12 example l18411: // assume cu rrent pc = 18411h. lnks 107h // call the subroutine at 18107h, with the current pc saved // in il (il[19:0] ? 18412h) if program size is 64k word or more. llnk cc:4, imm:20 saves the current pc in il and jumps to the program address specified by imm:20. since this is a 2-word instruction, the return address saved in il is (pc + 2). if the program size is less than 64k word when pc is saved, pc[19:16] is not saved in ilx. operation il[15:0] ? current pc + 2 if branch taken and program size is less than 64k word il[19:0] ? current pc + 2 if branch taken and program size is 64k word or more pc[15:0] ? imm[15:0] if branch taken and program size is less than 64k word pc[19:0] ? imm[19:0] if branch taken and program size is 64k word or more pc[11:0] ? pc[11:0] + 2 otherwise example l18411: // assume cur rent pc = 18411h. llnk nz, 10107h // call the subroutine at 10107h with the current pc saved // in il (il[19:0] ? 18413h) if program size is 64k word or more ret, iret returns from the current subroutine. iret sets ie (sr0[1]) in addition. if the program size is less than 64k word, pc[19:16] is not loaded from hs[19:16]. operation pc[15:0] ? hs[ sptr - 2] and sptr ? sptr - 2 (pop stack) if program size is less than 64k word pc[19:0] ? hs[ sptr - 2] and sptr ? sptr - 2 (pop stack) if program size is 64k word or more example ret // assume sptr = 3h and hs[1] = 18407h. // the next pc will be 18407h and sptr is set to 1h
instruction set s3c k225/fk225 7- 24 lret returns from the current subroutine, using the link register il. if the program size is less than 64k word, pc[19:16] is not loaded from ilx. operation pc[15:0] ? il[15:0] if program size is less than 64k word pc[19:0] ? il[19:0] if program size is 64k word or more example lret // assume il = 18407h. // the next instruction to execute is at pc = 18407h // if program size is 64k word or more jp/lnk/call jp/lnk/call instructions are pseudo instructions. if jr/lnks/calls commands (1 word instructions) can access the target address, there is no conditional code in the case of call/lnk and the jp/lnk/call commands are assembled to jr/lnks/calls in linking time or else the jp/lnk/call commands are assembled to ljp/llnk/lcall (2 word instructions) instructions.
S3CK225/fk225 instr uction set 7- 25 bit manipulation instructions bitop adr:8.bs performs a bit operation specified by op on the value in the data memory pointed by adr:8 and stores the result into r3 of current gpr bank or back into memory depending on the value of tf bit. bitop = bits, bitr, bitc, bitt bits: bit set bitr: bit reset bitc: bit complement bitt: bit test (r3 is not touched in this case) bs: bit location specifier, 0 - 7. operation r3 ? dm[00h:adr:8] bitop bs if eid = 0 r3 ? dm[idh:adr:8] bitop bs if eid = 1 (no register transfer for bitt) set the zero (z) bit if the result is 0. example bits 25h.3 // assume eid = 0. set bit 3 of dm[00h:25h] and store the result in r3. bitt 25h.3 // check bit 3 of dm[00h:25h] if eid = 0. bmc/bms clears or sets the tf bit, which is used to determine the destination of bitop instructions. when tf bit is clear, the result of bitop instructions will be stored into r3 (fixed); if the tf bit is set, the result will be written back to memory. operation tf ? 0 (bmc) tf ? 1 (bms) tm gpr, #imm:8 performs and operation on gpr and imm:8 and sets the zero (z) and negative (n) bits. no change in gpr. operation z, n flag ? gpr & #imm:8 bitop gpr.bs performs a bit operation on gpr and stores the result in gpr. since the equivalent functionality can be achieved using or gpr, #imm:8, and gpr, #imm:8, and xor gpr, #imm:8, this instruction type doesn?t have separate op codes.
instruction set s3c k225/fk225 7- 26 and sr0, #imm:8/or sr0, #imm:8 sets/resets bits in sr0 and stores the result back into sr0. operation sr0 ? sr0 & #imm:8 sr0 ? sr0 | #imm:8 bank #imm:2 loads sr0[4:3] with # imm[1:0]. operation sr0[4:3] ? # imm[1:0] miscellaneous instruction swap gpr, spr swaps the values in gpr and spr. sr0 and sr1 can not be used for this instruction. no flag is updated, even though the destination is gpr. operation temp ? spr spr ? gpr gpr ? temp example swap r0, idh // assume idh = 00h and r0 = 08h. // after this, idh = 08h and r0 = 00h. push reg saves reg in the stack (pushes reg into stack). reg = gpr, spr operation hs[ sptr][7:0] ? reg and sptr ? sptr + 1 example push r0 // assume r0 = 08h and sptr = 2h // then hs[2][7:0] ? 08h and sptr ? 3h
S3CK225/fk225 instr uction set 7- 27 pop reg pops stack into reg. reg = gpr, spr operation reg ? hs[sptr-1][7:0] and sptr ? sptr ? 1 example pop r0 // assume sptr = 3h and hs[2] = 18407h // r0 ? 07h and sptr ? 2h pop pops 2 bytes from the stack and discards the popped data. nop does no work but increase pc by 1. break does nothing and does not increment pc. this instruction is for the debugger only. when this instruction is executed, the processor is locked since pc is not incremented. therefore, this instruction should not be used under any mode other than the debug mode. sys #imm:8 does nothing but increase pc by 1 and generates syscp[7:0] and nsysid signals. cld gpr, imm:8 gpr ? (imm:8) and generates syscp[7:0], ncldid, and ncldwr signals. cld imm:8, gpr (imm:8) ? gpr and generates syscp[7:0], ncldid, and ncldwr signals. cop #imm:12 generates syscp[11:0] and ncopid signals.
instruction set s3c k225/fk225 7- 28 ldc loads program memory item into register. operation [tbh:tbl] ? pm[ilx:ilh:ill] (ldc @il) [tbh:tbl] ? pm[ilx:ilh:ill], ill++ (ldc @il+) tbh and tbl are temporary registers to hold the transferred program memory items. these can be accessed only by ld gpr and tbl/tbh instruction. example ld ilx, r1 // assume r1:r2:r3 has the program address to access ld ilh, r2 ld ill, r3 ldc @il // get the program data @(ilx:ilh:ill) into tbh:tbl
S3CK225/fk225 instr uction set 7- 29 pseudo instructions ei/di exceptions enable and disable instruction. operation sr0 ? or sr0,#00000010b (ei) sr0 ? and sr0,#11111101b (di) exceptions are enabled or disabled through this instruction. if there is an ei instruction, the sr0.1 is set and reset, when di instruction. example di ei scf/rcf carry flag set and reset instruction. operation cp r0,r0 (scf) and r0,r0 (rcf) carry flag is set or reset through this instruction. if there is an scf instruction, the sr1.0 is set and reset, when rcf instruction. example scf rcf stop/idle mcu power saving instruction. operation sys #0ah (stop) sys #05h (idle) the stop instruction stops the both cpu clock and system clock and causes the microcontroller to enter stop mode. the idle instruction stops the cpu clock while allowing system clock oscillation to continue. example stop(or idle) nop nop nop
instruction set s3c k225/fk225 7- 30 adc ? add with carry format: adc , : gpr : adr:8, gpr operation: ? + + c adc adds the values of and and carry (c) and stores the result back into flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. . n: exclusive or of v and msb of result. example: adc r0, 80h // if eid = 0, r0 ? r0 + dm[0080h] + c // if eid = 1, r0 ? r0 + dm[idh:80h] + c adc r0, r1 // r0 ? r0 + r1 + c add r0, r2 adc r1, r3 in the last two instructions, assuming that register pair r1:r0 and r3:r2 are 16-bit signed or unsigned numbers. even if the result of ?add r0, r2? is not zero, z flag can be set to ?1? if the result of ?adc r1,r3? is zero. note that zero (z) flag do not exactly reflect result of 16-bit operation. therefore when programming 16-bit addition, take care of the change of z flag.
S3CK225/fk225 instr uction set 7- 31 add ? add format: add , : gpr : adr:8, #imm:8, gpr, @ idm operation: ? + add adds the values of and and stores the result back into . flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. . n: exclusive or of v and msb of result. example: given: idh:idl0 = 80ffh, eid = 1 add r0, 80h // r0 ? r0 + dm[8080h] add r0, #12h // r0 ? r0 + 12h add r1, r2 // r1 ? r1 + r2 add r0, @id0 + 2 // r0 ? r0 + dm[80ffh], idh ? 81h, idl0 ? 01h add r0, @[id0 ? 3] // r0 ? r0 + dm[80fch], idh ? 80h, idl0 ? fch add r0, @[id0 + 2]! // r0 ? r0 + dm[8101h], idh ? 80h, idl0 ? ffh add r0, @[id0 ? 2]! // r0 ? r0 + dm[80fdh], idh ? 80h, idl0 ? ffh in the last two instructions, the value of idh:idl0 is not changed. refer to table 7-5 for more detailed explanation about this addressing mode. idm = idx+offset:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! ( idx = id0 or id1)
instruction set s3c k225/fk225 7- 32 and ? bit-wise and format: and , : gpr : adr:8, #imm:8, gpr, @ idm operation: ? & and performs bit-wise and on the values in and and stores the result in . flags: z: set if result is zero. reset if not. n: set if the msb of result is 1. reset if not. example: given: idh:idl0 = 01ffh, eid = 1 and r0, 7ah // r0 ? r0 & dm[017ah] and r1, #40h // r1 ? r1 & 40h and r0, r1 // r0 ? r0 & r1 and r1, @id0 + 3 // r1 ? r1 & dm[01ffh], idh:idl0 ? 0202h and r1, @[id0 ? 5] // r1 ? r1 & dm[01fah], idh:idl0 ? 01fah and r1, @[id0 + 7]! // r1 ? r1 & dm[0206h], idh:idl0 ? 01ffh and r1, @[id0 ? 2]! // r1 ? r1 & dm[01fdh], idh:idl0 ? 01ffh in the first instruction, if eid bit in sr0 is zero, register r0 has garbage value because data memory dm[0051h-007fh] are not mapped in s3cb519/s3fb519. in the last two instructions, the value of idh:idl0 is not changed. refer to table 7-5 for more detailed explanation about this addressing mode. idm = idx+offset:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! ( idx = id0 or id1)
S3CK225/fk225 instr uction set 7- 33 and sr0 ? bit-wise and with sr0 format: and sr0, #imm:8 operation: sr0 ? sr0 & imm:8 and sr0 performs the b it-wise and operation on the value of sr0 and imm:8 and stores the result in sr0. flags: ? example: given: sr0 = 11000010b nie equ ~02h nie0 equ ~40h nie1 equ ~80h and sr0, # nie | nie0 | nie1 and sr0, #11111101b in the first example, the statement ?and sr0, #nie|nie0|nie1? clear all of bits of the global interrupt, interrupt 0 and interrupt 1. on the contrary, cleared bits can be set to ?1? by instruction ?or sr0, #imm:8?. refer to instruction or sr0 for more detailed explanation about enabling bit. in the second example, the statement ?and sr0, #11111101b? is equal to instruction di, which is disabling interrupt globally.
instruction set s3c k225/fk225 7- 34 bank ? gpr bank selection format: bank #imm:2 operation: sr0[4:3] ? imm:2 flags: ? note: for explanation of the calmrisc banked register file and its usage, please refer to chapter 3. example: bank #1 // select register bank 1 ld r0, #11h // bank1?s r0 ? 11h bank #2 // select register bank 2 ld r1, #22h // bank2?s r1 ? 22h
S3CK225/fk225 instr uction set 7- 35 bitc ? bit complement format: bitc adr:8.bs bs: 3-digit bit specifier operation: r3 ? ((adr:8) ^ (2**bs)) if (tf == 0) (adr:8) ? ((adr:8) ^ (2**bs)) if (tf == 1) bitc complements the specified bit of a value read from memory and stores the result in r3 or back into memory, depending on the value of tf. tf is set or clear by bms/bmc instruction. flags: z: set if result is zero. reset if not. note: since the destination register r3 is fixed, it is not specified explicitly. example: given: idh = 01, dm[0180h] = ffh, eid = 1 bmc // tf ? 0 bitc 80h.0 // r3 ? feh, dm[0180h] = ffh bms // tf ? 1 bitc 80h.1 // dm[0180h] ? fdh
instruction set s3c k225/fk225 7- 36 bitr ? bit reset format: bitr adr:8.bs bs: 3-digit bit specifier operation: r3 ? ((adr:8) & ((11111111) 2 - (2**bs))) if (tf == 0) (adr:8) ? ((adr:8) & ((11111111) 2 - (2**bs))) if (tf == 1) bitr resets the specified bit of a value read from memory and stores the result in r3 or back into memory, depending on the value of tf. tf is set or clear by bms/bmc instruction. flags: z: set if result is zero. reset if not. note: since the destination register r3 is fixed, it is not specified explicitly. example: given: idh = 01, dm[0180h] = ffh, eid = 1 bmc // tf ? 0 bitr 80h.1 // r3 ? fdh, dm[0180h] = ffh bms // tf ? 1 bitr 80h.2 // dm[0180h] ? fbh
S3CK225/fk225 instr uction set 7- 37 bits ? bit set format: bits adr:8.bs bs: 3-digit bit specifier. operation: r3 ? ((adr:8) | (2**bs)) if (tf == 0) (adr:8) ? ((adr:8) | (2**bs)) if (tf == 1) bits sets the specified bit of a value read from memory and stores the result in r3 or back into memory, depending on the value of tf. tf is set or clear by bms/bmc instruction. flags: z: set if result is zero. reset if not. note: since the destination register r3 is fixed, it is not specified explicitly. example: given: idh = 01, dm[0180h] = f0h, eid = 1 bmc // tf ? 0 bits 80h.1 // r3 ? 0f2h, dm[0180h] = f0h bms // tf ? 1 bits 80h.2 // dm[0180h] ? f4h
instruction set s3c k225/fk225 7- 38 bitt ? bit test format: bitt adr:8.bs bs: 3-digit bit specifier. operation: z ? ~((adr:8) & (2**bs)) bitt tests the specified bit of a value read from memory. flags: z: set if result is zero. reset if not. example: given: dm[0080h] = f7h, eid = 0 bitt 80h.3 // z flag is set to ?1? jr z, %1 // jump to label %1 because condition is true. %1 bits 80h.3 nop
S3CK225/fk225 instr uction set 7- 39 bmc/bms ? tf bit clear/set format: bms/bmc operation: bmc/bms clears (sets) the tf bit. tf ? 0 if bmc tf ? 1 if bms tf is a single bit flag which determines the destination of bit operations, such as bitc, bitr, and bits. flags: ? note: bmc/bms are the only instructions that modify the content of the tf bit. example: bms // tf ? 1 bits 81h.1 bmc // tf ? 0 bitr 81h.2 ld r0, r3
instruction set s3c k225/fk225 7- 40 call ? conditional subroutine call (pseudo instruction) format: call cc:4, imm:20 call imm:12 operation: if calls can access the target address and there is no conditional code (cc:4), call command is assembled to calls (1-word instruction) in linking time, else the call is assembled to lcall (2-word instruction). example: call c, wait // hs[ sptr][15:0] ? current pc + 2, sptr ? sptr + 2 // 2-word instruction call 0088h // hs[ sptr][15:0] ? current pc + 1, sptr ? sptr + 2 // 1-word instruction wait: nop // address at 0088h nop nop nop nop ret
S3CK225/fk225 instr uction set 7- 41 calls ? call subroutine format: calls imm:12 operation: hs[ sptr][15:0] ? current pc + 1, sptr ? sptr + 2 if the program size is less than 64k word. hs[ sptr][19:0] ? current pc + 1, sptr ? sptr + 2 if the program size is equal to or over 64k word. pc[11:0] ? imm:12 calls unconditionally calls a subroutine residing at the address specified by imm:12. flags: ? example: calls wait wait: nop nop nop ret because this is a 1-word instruction, the saved returning address on stack is (pc + 1).
instruction set s3c k225/fk225 7- 42 cld ? load into coprocessor format: cld imm:8, : gpr operation: (imm:8) ? cld loads the value of into (imm:8), where imm:8 is used to access the external coprocessor's address space. flags: ? example: ah equ 00h al equ 01h bh equ 02h bl equ 03h cld ah, r0 // a[15:8] ? r0 cld al, r1 // a[7:0] ? r1 cld bh, r2 // b[15:8] ? r2 cld bl , r3 // b[7:0] ? r3 the registers a[15:0] and b[15:0] are arithmetic unit (au) registers of mac816. above instructions generate syscp[7:0], ncldid and cldwr signals to access mac816.
S3CK225/fk225 instr uction set 7- 43 cld ? load from coprocessor format: cld , imm:8 : gpr operation: ? (imm:8) cld loads a value from the coprocessor, whose address is specified by imm:8. flags: z: set if the loaded value in is zero. reset if not. n: set if the msb of the loaded value in is 1. reset if not. example: ah equ 00h al equ 01h bh equ 02h bl equ 03h cld r0, ah // r0 ? a[15:8] cld r1, al // r1 ? a[7:0] cld r2, bh // r2 ? b[15:8] cld r3, bl // r3 ? b[7:0] the registers a[15:0] and b[15:0] are arithmetic uni t (au) registers of mac816. above instructions generate syscp[7:0], ncldid and cldwr signals to access mac816.
instruction set s3c k225/fk225 7- 44 com ? 1's or bit-wise complement format: com : gpr operation: ? ~ com takes the bit-wise complement operation on and stores the result in . flags: z: set if result is zero. reset if not. n: set if the msb of result is 1. reset if not. example: given: r1 = 5ah com r1 // r1 ? a5h, n flag is set to ?1?
S3CK225/fk225 instr uction set 7- 45 com2 ? 2's complement format: com2 : gpr operation: ? ~ + 1 com2 computes the 2's complement of and stores the result in . flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. n: set if result is negative. example: given: r0 = 00h, r1 = 5ah com2 r0 // r0 ? 00h, z and c flags are set to ?1?. com2 r1 // r1 ? a6h, n flag is set to ?1?.
instruction set s3c k225/fk225 7- 46 comc ? bit-wise complement with carry format: comc : gpr operation: ? ~ + c comc takes the bit-wise complement of , adds carry and stores the result in . flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. n: set if result is negative. reset if not. example: if register pair r1:r0 is a 16-bit number, then the 2?s complement of r1:r0 can be obtained by com2 and comc as following. com2 r0 comc r1 note that z flag do not exactly reflect result of 16-bit operation. for example, if 16-bit register pair r1: r0 has value of ff01h, then 2?s complement of r1: r0 is made of 00ffh by com2 and comc. at this time, by instruction comc, zero (z) flag is set to ?1? as if the result of 2?s complement for 16-bit number is zero. therefore when programming 16-bit comparison, take care of the change of z flag.
S3CK225/fk225 instr uction set 7- 47 cop ? coprocessor format: cop #imm:12 operation: cop passes imm:12 to the coprocessor by generating syscp[11:0] and ncopid signals. flags: ? example: cop #0d01h // generate 1 word instruction code(fd01h) cop #0234h // generate 1 word instruction code(f234h) the above two instructions are equal to statement ?eld a, #1234h? for mac816 operation. the microcode of mac instruction ?eld a, #1234h? is ?fd01f234?, 2-word instruction. in this, code ?f? indicates ?cop? instruction.
instruction set s3c k225/fk225 7- 48 cp ? compare format: cp , : gpr : adr:8, #imm:8, gpr, @ idm operation: + ~ + 1 cp compares the values of and by subtracting from . contents of and are not changed. flags: c: set if carry is generated. reset if not. z: set if result is zero (i.e., and are same). reset if not. v: set if overflow is generated. reset if not. n: set if result is negative. reset if not. example: given: r0 = 73h, r1 = a5h, idh:idl0 = 0123h, dm[0123h] = a5, eid = 1 cp r0, 80h // c flag is set to ?1? cp r0, #73h // z and c flags are set to ?1? cp r0, r1 // v flag is set to ?1? cp r1, @id0 // z and c flags are set to ?1? cp r1, @[id0 ? 5] cp r2, @[id0 + 7]! cp r2, @[id0 ? 2]! in the last two instructions, the value of idh:idl0 is not changed. refer to table 7-5 for more detailed explanation about this addressing mode. idm = idx+offset:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! ( idx = id0 or id1)
S3CK225/fk225 instr uction set 7- 49 cpc ? compare with carry format: cpc , : gpr : adr:8, gpr operation: ? + ~ + c cpc compares and by subtracting from . unlike cp, however, cpc adds (c - 1) to the result. contents of and are not changed. flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. n: set if result is negative. reset if not. example: if register pair r1:r0 and r3:r2 are 16-bit signed or unsigned numbers, then use cp and cpc to compare two 16-bit numbers as follows. cp r0, r1 cpc r2, r3 because cpc considers c when comparing and , cp and cpc can be used in pair to compare 16-bit operands. but note that zero (z) flag do not exactly reflect result of 16-bit operation. therefore when programming 16-bit comparison, take care of the change of z flag.
instruction set s3c k225/fk225 7- 50 dec ? decrement format: dec : gpr operation: ? + 0ffh dec decrease the value in by adding 0ffh to . flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. n: set if result is negative. reset if not. example: given: r0 = 80h, r1 = 00h dec r0 // r0 ? 7fh, c, v and n flags are set to ?1? dec r1 // r1 ? ffh, n flags is set to ?1?
S3CK225/fk225 instr uction set 7- 51 decc ? decrement with carry format: decc : gpr operation: ? + 0ffh + c decc decrease the value in when carry is not set. when there is a carry, there is no change in the value of . flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. n: set if result is negative. reset if not. example: if register pair r1:r0 is 16-bit signed or unsigned numbe r, then use dec and decc to decrement 16-bit number as follows. dec r0 decc r1 note that zero (z) flag do not exactly reflect result of 16-bit operation. therefore when programming 16-bit decrement, take care of the change of z flag.
instruction set s3c k225/fk225 7- 52 di ? disable interrupt (pseudo instruction) format: di operation: disables interrupt globally. it is same as ?and sr0, #0fdh? . di instruction sets bit1 ( ie: global interrupt enable) of sr0 register to ?0? flags: ? example: given: sr0 = 03h di // sr0 ? sr0 & 11111101b di instruction clears sr0[1] to ?0?, disabling interrupt processing.
S3CK225/fk225 instr uction set 7- 53 ei ? enable interrupt (pseudo instruction) format: ei operation: enables interrupt globally. it is same as ?or sr0, #02h? . ei instruction sets the bit1 ( ie: global interrupt enable) of sr0 register to ?1? flags: ? example: given: sr0 = 01h ei // sr0 ? sr0 | 00000010b the statement ?ei? sets the sr0[1] to ?1?, enabling all interrupts.
instruction set s3c k225/fk225 7- 54 idle ? idle operation (pseudo instruction) format: idle operation: the idle instruction stops the cpu clock while allowing system clock oscillation to continue. idle mode can be released by an interrupt or reset operation. the idle instruction is a pseudo instruction. it is assembled as ?sys #05h?, and this generates the syscp[7-0] signals. then these signals are decoded and the decoded signals execute the idle operation. flags: ? note: the next instruction of idle instruction is executed, so please use the nop instruction after the idle instruction. example: idle nop nop nop the idle instruction stops the cpu clock but not the system clock.
S3CK225/fk225 instr uction set 7- 55 inc ? increment format: inc : gpr operation: ? + 1 inc increase the value in . flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. n: set if result is negative. reset if not. example: given: r0 = 7fh, r1 = ffh inc r0 // r0 ? 80h, v flag is set to ?1? inc r1 // r1 ? 00h, z and c flags are set to ?1?
instruction set s3c k225/fk225 7- 56 incc ? increment with carry format: incc : gpr operation: ? + c incc increase the value of only if there is carry. when there is no carry, the value of is not changed. flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. n: exclusive or of v and msb of result. example: if register pair r1:r0 is 16-bit signed or unsigned number, then use inc and incc to increment 16-bit number as following. inc r0 incc r1 assume r1:r0 is 0010h, statement ?inc r0? increase r0 by one without carry and statement ?incc r1? set zero (z) flag to ?1? as if the result of 16-bit increment is zero. note that zero (z) flag do not exactly reflect result of 16-bit operation. therefore when programming 16-bit increment, take care of the change of z flag.
S3CK225/fk225 instr uction set 7- 57 iret ? return from interrupt handling format: iret operation: pc ? hs[ sptr - 2], sptr ? sptr - 2 iret pops the return address (after interrupt handling) from the hardware stack and assigns it to pc. the ie (i.e., sr0[1]) bit is set to allow further interrupt generation. flags: ? note: the program size (indicated by the np64kw signal) determines which portion of pc is updated. when the program size is less than 64k word, only the lower 16 bits of pc are updated (i.e., pc[15:0] ? hs[ sptr ? 2] ) . when the program size is 64k word or more, the action taken is pc[19:0] ? hs[ sptr - 2]. example: sf_excep: nop // stack full exception service routine iret
instruction set s3c k225/fk225 7- 58 jnzd ? jump not zero with delay slot format: jnzd , imm:8 : gpr (bank 3?s gpr only) imm:8 is an signed number operation: pc ? pc[delay slot] - 2?s complement of imm:8 ? - 1 jnzd performs a backward pc-relative jump if evaluates to be non-zero. furthermore, jnzd decrease the value of . the instruction immediately following jnzd (i.e., in delay slot) is always executed, and this instruction must be 1 cycle instruction. flags: ? note: typically, the delay slot will be filled with an instruction from the loop body. it is noted, however, that the chosen instruction should be ?dead? outside the loop for it executes even when the loop is exited (i.e., jnzd is not taken). example: given: idh = 03h, eid = 1 bank #3 ld r0, #0ffh // r0 is used to loop counter ld r1, #0 %1 ld idl0, r0 jnzd r0, %b1 // if r0 of bank3 is not zero, jump to %1. ld @id0, r1 // clear register point ed by id0 this example can be used for ram clear routine. the last instruction is executed even if the loop is exited.
S3CK225/fk225 instr uction set 7- 59 jp ? conditional jump (pseudo instruction) format: jp cc:4 imm:20 jp cc:4 imm:9 operation: if jr can access the target address, jp command is assembled to jr (1 word instruction) in linking time, else the jp is assembled to ljp (2 word instruction) instruction. there are 16 different conditions that can be used, as described in table 7-6. example: %1 ld r0, #10h // assume address of label %1 is 020dh jp z, %b1 // address at 0264h jp c, %f2 // address at 0265h %2 ld r1, #20h // assume address of label %2 is 089ch in the above example, the statement ?jp z, %b1? is assembled to jr instruction. assuming that current pc is 0264h and condition is true, next pc is made by pc[11:0] ? pc[11:0] + offset, offset value is ?64h + a9h? without carry. ?a9? means 2?s complement of offset value to jump backward. therefore next pc is 020dh. on the other hand, statement ?jp c, %f2? is assembled to ljp instruction because offset address exceeds the range of imm:9.
instruction set s3c k225/fk225 7- 60 jr ? conditional jump relative format: jr cc:4 imm:9 cc:4: 4-bit condition code operation: pc[11:0] ? pc[11:0] + imm:9 if condition is true. imm:9 is a signed number, which is sign- extended to 12 bits when added to pc. there are 16 different conditions that can be used, as described in table 7-6. flags: ? note: unlike ljp, the target address of jr is pc-relative. in the case of jr, imm:9 is added to pc to compute the actual jump address, while ljp directly jumps to imm:20, the target. example: jr z, %1 // assume current pc = 1000h %1 ld r0, r1 // address at 10a5h after the first instruction is executed, next pc has become 10a5h if z flag bit is set to ?1?. the range of the relative address is from +255 to ?256 because imm:9 is signed number.
S3CK225/fk225 instr uction set 7- 61 lcall ? conditional subroutine call format: lcall cc:4, imm:20 operation: hs[ sptr][15:0] ? current pc + 2, sptr ? sptr + 2, pc[15:0] ? imm[15:0] if the condition holds and the program size is less than 64k word. hs[ sptr][19:0] ? current pc + 2, sptr ? sptr + 2, pc[19:0] ? imm:20 if the condition holds and the program size is equal to or over 64k word. pc[11:0] ? pc[11:0] + 2 otherwise. lcall instruction is used to call a subroutine whose starting address is specified by imm:20. flags: ? example: lcall l1 lcall c, l2 label l1 and l2 can be allocated to the same or other section. because this is a 2-word instruction, the saved returning address on stack is (pc + 2).
instruction set s3c k225/fk225 7- 62 ld adr:8 ? load into memory format: ld adr:8, : gpr operation: dm[00h:adr:8] ? if eid = 0 dm[idh:adr:8] ? if eid = 1 ld adr:8 loads the value of into a memory location. the memory location is determined by the eid bit and adr:8. flags: ? example: given: idh = 01h ld 80h, r0 if eid bit of sr0 is zero, the statement ?ld 80h, r0? load value of r0 into dm[0080h], else eid bit was set to ?1?, the statement ?ld 80h, r0? load value of r0 into dm[0180h]
S3CK225/fk225 instr uction set 7- 63 ld @ idm ? load into memory indexed format: ld @ idm, : gpr operation: (@ idm) ? ld @ idm loads the value of into the memory location determined by @ idm. details of the @ idm format and how the actual address is calculated can be found in chapter 2. flags: ? example: given r0 = 5ah, idh:idl0 = 8023h, eid = 1 ld @id0, r0 // dm[8023h] ? 5ah ld @id0 + 3, r0 // dm[8023h] ? 5ah, idl0 ? 26h ld @[id0- 5], r0 // dm[801eh] ? 5ah, idl0 ? 1eh ld @[id0+4]!, r0 // dm[8027h] ? 5ah, idl0 ? 23h ld @[id0-2]!, r0 // dm[8021h] ? 5ah, idl0 ? 23h in the last two instructions, the value of idh:idl0 is not changed. refer to table 7-5 for more detailed explanation about this addressing mode. idm = idx+offset:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! ( idx = id0 or id1)
instruction set s3c k225/fk225 7- 64 ld ? load register format: ld , : gpr : gpr, spr, adr:8, @ idm, #imm:8 operation: ? ld loads a value specified by into the register designated by . flags: z: set if result is zero. reset if not. n: exclusive or of v and msb of result. example: given: r0 = 5ah, r1 = aah, idh:idl0 = 8023h, eid = 1 ld r0, r1 // r0 ? aah ld r1, idh // r1 ? 80h ld r2, 80h // r2 ? dm[8080h] ld r0, #11h // r0 ? 11h ld r0, @id0+1 // r0 ? dm[8023h], idl0 ? 24h ld r1, @[id0-2] // r1 ? dm[8021h], idl0 ? 21h ld r2, @[id0+3]! // r2 ? dm[8026h], idl0 ? 23h ld r3, @[ id0-5]! // r3 ? dm[801eh], idl0 ? 23h in the last two instructions, the value of idh:idl0 is not changed. refer to table 7-5 for more detailed explanation about this addressing mode. idm = idx+offset:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! ( idx = id0 or id1)
S3CK225/fk225 instr uction set 7- 65 ld ? load gpr:bankd, gpr:banks format: ld , : gpr: bankd : gpr: banks operation: ? ld loads a value of a register in a specified bank (banks) into another register in a specified bank ( bankd). flags: z: set if result is zero. reset if not. n: exclusive or of v and msb of result. example: ld r2:1, r0:3 // bank1?s r2 ? bank3?s r0 ld r0:0, r0:2 // bank0?s r0 ? bank2?s r0
instruction set s3c k225/fk225 7- 66 ld ? load gpr, tbh/tbl format: ld , : gpr : tbh/tbl operation: ? ld loads a value specified by into the register designated by . flags: z: set if result is zero. reset if not. n: exclusive or of v and msb of result. example: given: register pair r1:r0 is 16-bit unsigned data. ldc @il // tbh:tbl ? pm[ilx:ilh:ill] ld r1, tbh // r1 ? tbh ld r0, tbl // r0 ? tbl
S3CK225/fk225 instr uction set 7- 67 ld ? load tbh/tbl, gpr format: ld , : tbh/tbl : gpr operation: ? ld loads a value specified by into the register designated by . flags: ? example: given: register pair r1:r0 is 16-bit unsigned data. ld tbh, r1 // tbh ? r1 ld tbl, r0 // tbl ? r0
instruction set s3c k225/fk225 7- 68 ld spr ? load spr format: ld , : spr : gpr operation: ? ld spr loads the value of a gpr into an spr. refer to table 3-1 f or more detailed explanation about kind of spr. flags: ? example: given: register pair r1:r0 = 1020h ld ilh, r1 // ilh ? 10h ld ill, r0 // ill ? 20h
S3CK225/fk225 instr uction set 7- 69 ld spr0 ? load spr0 immediate format: ld spr0, #imm:8 operation: spr0 ? imm:8 ld spr0 loads an 7-bit immediate value into spr0. flags: ? example: given: eid = 1, idb = 0 (index register bank 0 selection) ld idh, #80h // idh point to page 80h ld idl1, #44h ld idl0, #55h ld sr0, #02h the last instruction set ie (global interrupt enable) bit to ?1?. special register group 1 (spr1) registers are not supported in this addressing mode.
instruction set s3c k225/fk225 7- 70 ldc ? load code format: ldc : @il, @il+ operation: tbh:tbl ? pm[ilx:ilh:ill] ill ? ill + 1 (@il+ only) ldc loads a data item from program memory and stores it in the tbh:tbl register pair. @il+ increase the value of ill, efficiently implementing table lookup operations. flags: ? example: ld ilx, r1 ld ilh, r2 ld ill, r3 ldc @il // loads value of pm[ilx:ilh:ill] into tbh:tbl ld r1, tbh // move data in tbh:tbl to gprs for further processing ld r0, tbl the statement ?ldc @il? do not increase, but if you use statement ?ldc @il+?, ill register is increased by one after instruction execution.
S3CK225/fk225 instr uction set 7- 71 ljp ? conditional jump format: ljp cc:4, imm:20 cc:4: 4-bit condition code operation: p c[15:0] ? imm[15:0] if condition is true and the program size is less than 64k word. if the program is equal to or larger than 64k word, pc[19:0] ? imm[19:0] as long as the condition is true. there are 16 different conditions that can be used, as described in table 7-6. flags: ? note: ljp cc:4 imm:20 is a 2-word instruction whose immediate field directly specifies the target address of the jump. example: ljp c, %1 // assume current pc = 0812 h %1 ld r0, r1 // address at 10a5h after the first instruction is executed, ljp directly jumps to address 10a5h if condition is true.
instruction set s3c k225/fk225 7- 72 llnk ? linked subroutine call conditional format: llnk cc:4, imm:20 cc:4: 4-bit condition code operation: if condition is true, il[19:0] ? {pc[19:12], pc[11:0] + 2}. further, when the program is equal to or larger than 64k word, pc[19:0] ? imm[19:0] as long as the condition is true. if the program is smaller than 64k word, pc[15:0] ? imm[15:0]. there are 16 different conditions that can be used, as described in table 7-6. flags: ? note: llnk is used to conditionally to call a subroutine with the return address saved in the link register (il) without stack operation. this is a 2-word instruction. example: llnk z, %1 // address at 005ch, ilx:ilh:ill ? 00:00:5eh nop // address at 005eh %1 ld r0, r1 lret
S3CK225/fk225 instr uction set 7- 73 lnk ? linked subroutine call (pseudo instruction) format: lnk cc:4, imm:20 lnk imm:12 operation: if lnks can access the target address and there is no conditional code (cc:4), lnk command is assembled to lnks (1 word instruction) in linking time, else the lnk is assembled to llnk (2 word instruction). example: lnk z, link1 // equal to ?llnk z, link1? lnk link2 // equal to ?lnks link2? nop link2: nop lret subroutines section code, abs 0a00h subroutines link1: nop lret
instruction set s3c k225/fk225 7- 74 lnks ? linked subroutine call format: lnks imm:12 operation: il[19:0] ? {pc[19:12], pc[11:0] + 1} and pc[11:0] ? imm:12 lnks saves the current pc in the link register and jumps to the address specified by imm:12. flags: ? note: lnks is used to call a subroutine with the return address saved in the link register (il) without stack operation. example: lnks link1 // address at 005ch, ilx:ilh:ill ? 00:00:5dh nop // address at 005dh link1: nop lret
S3CK225/fk225 instr uction set 7- 75 lret ? return from linked subroutine call format: lret operation: pc ? il[19:0] lret returns from a subroutine by assigning the saved return address in il to pc. flags: ? example: lnk link1 link1: nop lret ; pc[19:0] ? ilx:ilh:ill
instruction set s3c k225/fk225 7- 76 nop ? no operation format: nop operation: no operation. when the instruction nop is executed in a program, no operation occurs. instead, the instruction time is delayed by approximately one machine cycle per each nop instruction encountered. flags: ? example: nop
S3CK225/fk225 instr uction set 7- 77 or ? bit-wise or format: or , : gpr : adr:8, #imm:8, gpr, @ idm operation: ? | or performs the bit-wise or operation on and and stores the result in . flags: z: set if result is zero. reset if not. n: exclusive or of v and msb of result. example: given: idh:idl0 = 031eh, eid = 1 or r0, 80h // r0 ? r0 | dm[0380h] or r1, #40h // mask bit6 of r1 or r1, r0 // r1 ? r1 | r0 or r0, @id0 // r0 ? r0 | dm[031eh], idl0 ? 1eh or r1, @[id0-1] // r1 ? r1 | dm[031dh], idl0 ? 1dh or r2, @[id0+1]! // r2 ? r2 | dm[031fh], idl0 ? 1eh or r3, @[id0-1]! // r3 ? r3 | dm[031dh], idl0 ? 1eh in the last two instructions, the value of idh:idl0 is not changed. refer to table 7-5 for more detailed explanation about this addressing mode. idm = idx+offset:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! ( idx = id0 or id1)
instruction set s3c k225/fk225 7- 78 or sr0 ? bit-wise or with sr0 format: or sr0, #imm:8 operation: sr0 ? sr0 | imm:8 or sr0 performs the bit-wise or operation on sr0 and imm:8 and stores the result in sr0. flags: ? example: given: sr0 = 00000000b eid equ 01h ie equ 02h idb1 equ 04h ie0 equ 40h ie1 equ 80h or sr0, #ie | ie0 | ie1 or sr0, #00000010b in the first example, the statement ?or sr0, #eid|ie|ie0? set global interrupt( ie), interrupt 0(ie0) and interrupt 1(ie1) to ?1? in sr0. on the contrary, enabled bits can be cleared with instruction ?and sr0, #imm:8?. refer to instruction and sr0 for more detailed explanation about disabling bit. in the second example, the statement ?or sr0, #00000010b? is equal to instruction ei, which is enabling interrupt globally.
S3CK225/fk225 instr uction set 7- 79 pop ? pop format: pop operation: sptr ? sptr ? 2 pop decrease sptr by 2. the top two bytes of the hardware stack are therefore invalidated. flags: ? example: given: sptr[5:0] = 001010b pop this pop instruction decrease sptr[5:0] by 2. therefore sptr[5:0] is 001000b.
instruction set s3c k225/fk225 7- 80 pop ? pop to register format: pop : gpr, spr operation: ? hs[ sptr - 1], sptr ? sptr - 1 pop copies the value on top of the stack to and decrease sptr by 1. flags: z: set if the value copied to is zero. reset if not. n: set if the value copied to is negative. reset if not. when is spr, no flags are affected, including z and n. example: pop r0 // r0 ? hs[sptr-1], sptr ? sptr-1 pop idh // idh ? hs[sptr-1], sptr ? sptr-1 in the first instruction, value of hs[sptr-1] is loaded to r0 and the second instruction ?pop idh? load value of hs[sptr-1] to register idh. refer to chapter 5 for more detailed explanation about pop operations for hardware stack.
S3CK225/fk225 instr uction set 7- 81 push ? push register format: push : gpr, spr operation: hs[ sptr] ? , sptr ? sptr + 1 push stores the value of on top of the stack and increase sptr by 1. flags: ? example: push r0 // hs[ sptr] ? r0, sptr ? sptr + 1 push idh // hs[ sptr] ? idh, sptr ? sptr + 1 in the first instruction, value of register r0 is loaded to hs[sptr-1] and the second instruction ?push idh? load value of register idh to hs[sptr-1]. current hs pointed by stack point sptr[5:0] be emptied. refer to chapter 5 for more detailed explanation about push operations for hardware stack.
instruction set s3c k225/fk225 7- 82 ret ? return from subroutine format: ret operation: pc ? hs[ sptr - 2], sptr ? sptr ? 2 ret pops an address on the hardware stack into pc so that control returns to the subroutine call site. flags: ? example: given: sptr[5:0] = 001010b calls wait / / address at 00120h wait: nop // address at 01000h nop nop nop nop ret after the first instruction calls execution, ?pc+1?, 0121h is loaded to hs[5] and hardware stack pointer sptr[5:0] have 001100b and next pc became 01000h. the instruction ret pops value 0121h on the hardware stack hs[sptr-2] and load to pc then stack pointer sptr[[5:0] became 001010b.
S3CK225/fk225 instr uction set 7- 83 rl ? rotate left format: rl < op>: gpr operation: c ? [7], ? {[6:0], [7]} rl rotates the value of to the left and stores the result back into . the original msb of is copied into carry (c). flags: c: set if the msb of (before rotating) is 1. reset if not. z: set if result is zero. reset if not. n: set if the msb of (after rotating) is 1. reset if not. example: given: r0 = 01001010b, r1 = 10100101b rl r0 // n flag is set to ?1?, r0 ? 10010100b rl r1 // c flag is set to ?1?, r1 ? 01001011b
instruction set s3c k225/fk225 7- 84 rlc ? rotate left with carry format: rlc : gpr operation: c ? [7], ? {[6:0], c} rlc rotates the value of to the left and stores the result back into . the original msb of is copied into carry (c), and the original c bit is copied into [0]. flags: c: set if the msb of (before rotating) is 1. reset if not. z: set if result is zero. reset if not. n: set if the msb of (after rotating) is 1. reset if not. example: given: r2 = a5h, if c = 0 rlc r2 // r2 ? 4ah, c flag is set to ?1? rl r0 rlc r1 in the second example, assuming that register pair r1:r0 is 16-bit number, then rl and rlc are used for 16-bit rotate left operation. but note that zero (z) flag do not exactly reflect result of 16- bit operation. therefore when programming 16-bit decrement, take care of the change of z flag.
S3CK225/fk225 instr uction set 7- 85 rr ? rotate right format: rr : gpr operation: c ? [0], ? {[0], [7:1]} rr rotates the value of to the right and stores the result back into . the original lsb of is copied into carry (c). flags: c: set if the lsb of (before rotating) is 1. reset if not. z: set if result is zero. reset if not. n: set if the msb of (after rotating) is 1. reset if not. example: given: r0 = 01011010b, r1 = 10100101b rr r0 // no change of flag, r0 ? 00101101b rr r1 // c and n flags are set to ?1?, r1 ? 11010010b
instruction set s3c k225/fk225 7- 86 rrc ? rotate right with carry format: rrc : gpr operation: c ? [0], ? {c, [7:1]} rrc rotates the value of to the right and stores the result back into . the original lsb of is copied into carry (c), and c is copied to the msb. flags: c: set if the lsb of (before rotating) is 1. reset if not. z: set if result is zero. reset if not. n: set if the msb of (after rotating) is 1. reset if not. example: given: r2 = a5h, if c = 0 rrc r2 // r2 ? 52h, c flag is set to ?1? rr r0 rrc r1 in the second example, assuming that register pair r1:r0 is 16-bit number, then rr and rrc are used for 16-bit rotate right operation. but note that zero (z) flag do not exactly reflect result of 16-bit operation. therefore when programming 16-bit decrement, take care of the change of z flag.
S3CK225/fk225 instr uction set 7- 87 sbc ? subtract with carry format: sbc , : gpr : adr:8, gpr operation: ? + ~ + c sbc computes ( - ) when there is carry and ( - - 1) when there is no carry. flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. n: set if result is negative. reset if not. example: sbc r0, 80h // if eid = 0, r0 ? r0 + ~dm[0080h] + c // if eid = 1, r0 ? r0 + ~dm[idh:80h] + c sbc r0, r1 // r0 ? r0 + ~r1 + c sub r0, r2 sbc r1, r3 in the last two instructions, assuming that register pair r1:r0 and r3:r2 are 16-bit signed or unsigned numbers. even if the result of ?add r0, r2? is not zero, zero (z) flag can be set to ?1? if the result of ?sbc r1,r3? is zero. note that zero (z) flag do not exactly reflect result of 16-bit operation. therefore when programming 16-bit addition, take care of the change of z flag.
instruction set s3c k225/fk225 7- 88 sl ? shift left format: sl : gpr operation: c ? [7], ? {[6:0], 0} sl shifts to the left by 1 bit. the msb of the original is copied into carry (c). flags: c: set if the msb of (before shifting) is 1. reset if not. z: set if result is zero. reset if not. n: set if the msb of (after shifting) is 1. reset if not. example: given: r0 = 01001010b, r1 = 10100101b sl r0 // n flag is set to ?1?, r0 ? 10010100b sl r1 // c flag is set to ?1?, r1 ? 01001010b
S3CK225/fk225 instr uction set 7- 89 sla ? shift left arithmetic format: sla : gpr operation: c ? [7], ? {[6:0], 0} sla shifts to the left by 1 bit. the msb of the original is copied into carry (c). flags: c: set if the msb of (before shifting) is 1. reset if not. z: set if result is zero. reset if not. v: set if the msb of the result is different from c. reset if not. n: set if the msb of (after shifting) is 1. reset if not. example: given: r0 = aah sla r0 // c, v, n flags are set to ?1?, r0 ? 54h
instruction set s3c k225/fk225 7- 90 sr ? shift right format: sr : gpr operation: c ? [0], ? {0, [7:1]} sr shifts to the right by 1 bit. the lsb of the original (i.e., [0]) is copied into carry (c). flags: c: set if the lsb of (before shifting) is 1. reset if not. z: set if result is zero. reset if not. n: set if the msb of (after shifting) is 1. reset if not. example: given: r0 = 01011010b, r1 = 10100101b sr r0 // no change of flags, r0 ? 00101101b sr r1 // c flag is set to ?1?, r1 ? 01010010b
S3CK225/fk225 instr uction set 7- 91 sra ? shift right arithmetic format: sra : gpr operation: c ? [0], ? {[7], [7:1]} sra shifts to the right by 1 bit while keeping the sign of . the lsb of the original (i.e., [0]) is copied into carry (c). flags: c: set if the lsb of (before shifting) is 1. reset if not. z: set if result is zero. reset if not. n: set if the msb of (after shifting) is 1. reset if not. note: sra keeps the sign bit or the msb ([7]) in its original position. if sra is executed ?n? times, n significant bits will be set, followed by the shifted bits. example: given: r0 = 10100101b sra r0 // c, n flags are set to ?1?, r0 ? 11010010b sra r0 // n flag is set to ?1?, r0 ? 11101001b sra r0 // c, n flags are set to ?1?, r0 ? 11110100b sra r0 // n flags are set to ?1?, r0 ? 11111010b
instruction set s3c k225/fk225 7- 92 stop ? stop operation (pseudo instruction) format: stop operation: the stop instruction stops the both the cpu clock and system clock and causes the microcontroller to enter the stop mode. in the stop mode, the contents of the on-chip cpu registers, peripheral registers, and i/o port control and data register are retained. a reset operation or external or internal interrupts can release stop mode. the stop instruction is a pseudo instruction. it is assembled as ?sys #0ah?, which generates the syscp[7-0] signals. these signals are decoded and stop the operation. note: the next instruction of stop instruction is executed, so please use the nop instruction after the stop instruction. example: stop nop nop nop in this example, the nop instructions provide the necessary timing delay for oscillation stabilization before the next instruction in the program sequence is executed. refer to the timing diagrams of oscillation stabilization, as described in figure 17-3, 17-4
S3CK225/fk225 instr uction set 7- 93 sub ? subtract format: sub , : gpr : adr:8, #imm:8, gpr, @ idm operation: ? + ~ + 1 sub adds the value of with the 2's complement of to perform subtraction on and flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. n: set if result is negative. reset if not. example: given: idh:idl0 = 0150h, dm[0143h] = 26h, r0 = 52h, r1 = 14h, eid = 1 sub r0, 43h // r0 ? r0 + ~dm[0143h] + 1 = 2ch sub r1, #16h // r1 ? feh, n flag is set to ?1? sub r0, r1 // r0 ? r0 + ~r1 + 1 = 3eh sub r0, @id0+1 // r0 ? r0 + ~dm[0150h] + 1, idl0 ? 51h sub r0, @[id0-2] // r0 ? r0 + ~dm[014eh] + 1, idl0 ? 4eh sub r0, @[id0+3]! // r0 ? r0 + ~dm[0153h] + 1, idl0 ? 50h sub r0, @[id0-2]! // r0 ? r0 + ~dm[014eh] + 1, idl0 ? 50h in the last two instructions, the value of idh:idl0 is not changed. refer to table 7-5 for more detailed explanation about this addressing mode. the example in the sbc description shows how sub and sbc can be used in pair to subtract a 16-bit number from another. idm = idx+offset:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! ( idx = id0 or id1)
instruction set s3c k225/fk225 7- 94 swap ? swap format: swap , : gpr : spr operation: ? , ? swap swaps the values of the two operands. flags: ? note: among the sprs, sr0 and sr1 can not be used as . example: given: idh:idl0 = 8023h, r0 = 56h, r1 = 01h swap r1, idh // r1 ? 80h, idh ? 01h swap r0, idl0 // r0 ? 23h, idl0 ? 56h after execution of instructions, index registers idh:idl0 (id0) have address 0156h.
S3CK225/fk225 instr uction set 7- 95 sys ? system format: sys #imm:8 operation: sys generates syscp[7:0] and nsysid signals. flags: ? note: mainly used for system peripheral interfacing. example: sys #0ah sys #05h in t he first example, statement ?sys #0ah? is equal to stop instruction and second example ?sys #05h? is equal to idle instruction. this instruction does nothing but increase pc by one and generates syscp[7:0] and nsysid signals.
instruction set s3c k225/fk225 7- 96 tm ? test multiple bits format: tm , #imm:8 : gpr operation: tm performs the bit-wise and operation on and imm:8 and sets the flags. the content of is not changed. flags: z: set if result is zero. reset if not. n: set if result is negative. reset if not. example: given: r0 = 01001101b tm r0, #00100010b // z flag is set to ?1?
S3CK225/fk225 instr uction set 7- 97 xor ? exclusive or format: xor , : gpr : adr:8, #imm:8, gpr, @ idm operation: ? ^ xor performs the bit-wise exclusive-or operation on and and stores the result in . flags: z: set if result is zero. reset if not. n: set if result is negative. reset if not. example: given: idh:idl0 = 8080h, dm[8043h] = 26h, r0 = 52h, r1 = 14h, eid = 1 xor r0, 43h // r0 ? 74h xor r1, #00101100b // r1 ? 38h xor r0, r1 // r0 ? 46h xor r0, @id0 // r0 ? r0 ^ dm[8080h], idl0 ? 81h xor r0, @[id0-2] // r0 ? r0 ^ dm[807eh], idl0 ? 7eh xor r0, @[id0+3]! // r0 ? r0 ^ dm[8083h], idl0 ? 80h xor r0, @[id0-5]! // r0 ? r0 ^ dm[807bh], idl0 ? 80h in the last two instructions, the value of idh:idl0 is not changed. refer to table 7-5 for more detailed explanation about this addressing mode. idm = idx+offset:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! ( idx = id0 or id1)
instruction set s3c k225/fk225 7- 98 notes
S3CK225/fk225 clock circuit 8- 1 8 clock circuit system clock circuit the system clock circuit has the following components: ? external crystal, ceramic resonator, or rc oscillation source (or an external clock source) ? oscillator stop and wake-up functions ? programmable frequency divid er for the cpu clock (f osc divided by 1, 2, 4, 8, 16, 32, 64, 128) ? system clock control register, pcon ? oscillator control register, osccon ? main oscillator clock output control register, clocon x in x out c1 c2 S3CK225 figure 8-1. main oscillator circuit (crystal or ceramic oscillator)
clock circuit s3ck2 25/fk225 8- 2 x in x out S3CK225 figure 8-2. main oscillator circuit (rc oscillator) xt in xt out c1 c2 S3CK225 figure 8-3. sub oscillator circuit (crystal or ceramic oscillator)
S3CK225/fk225 clock circuit 8- 3 basic timer, timer/counter 0,1,2,3 watch timer lcd controller sio a/d converter d/a converter amplifiers int stop release 1/1 - 1/4096 frequency dividing circuit 1/1 1/16 1/32 1/64 1/128 1/2 1/4 1/8 stop release int main-system oscillator circuit selector 1 fx fxt sub-system oscillator circuit stop osccon.2 stop fxx selector 2 oscillator control circuit cpu stop signal by idle or stop cpu pcon.2 - .0 osccon.3 osccon.0 watch timer lcd controller sys #05h idle sys #0ah stop figure 8-4. system clock circuit diagram
clock circuit s3ck2 25/fk225 8- 4 power control register (pcon) 02h, r/w, reset: 04h msb lsb not used system clock selection bits: 000 = fxx/128 001 = fxx/64 010 = fxx/32 011 = fxx/16 100 = fxx/8 101 = fxx/4 110 = fxx/2 111 = fxx/1 .7 .6 .5 .4 .3 .2 .1 .0 figure 8-5. power control register (pcon) oscillator control register (osccon) 03h, r/w, reset: 00h msb lsb not used main oscillator control bit: 0 = main oscillator run 1 = main oscillator stop not used system clock source selection bit: 0 = main oscillator select 1 = sub oscillator select .7 .6 .5 .4 .3 .2 .1 .0 sub oscillator control bit: 0 = sub oscillator run 1 = sub oscillator stop figure 8-6. oscillator control register (osccon)
S3CK225/fk225 clock circuit 8- 5 mux p7con.7-.6 p7.3/clkout clocon.0 fx figure 8-7. main oscillator clock output functional block diagram main oscillator clock output control register (clocon) 72h, r/w, reset: 00h msb lsb not used main oscillator clock level selection bit: 0 = fx level select 1 = inverted fx level select .7 .6 .5 .4 .3 .2 .1 .0 figure 8-8. main oscillator clock output control register (clocon)
clock circuit s3ck2 25/fk225 8- 6 notes
S3CK225/fk225 reset and power-down 9- 1 9 reset and power-dow n overview during a power-on reset, the voltage at v dd goes to high level and the reset pin is forced to low level. the reset signal is input through a schmitt trigger circuit where it is then synchronized with the cpu clock. this procedure brings mcu into a known operating status. for the time for cpu clock oscillation to stabilize, the reset pin must be held to low level for a minimum time interval after the power supply comes within tolerance. for the minimum time interval, see the electrical characteristics. in summary, the following sequence of events occurs during a reset operation: ? all interrupts are disabled. ? the watchdog function (basic timer) is enabled. ? ports are set to input mode. ? peripheral control and data registers are disabled and reset to their default hardware values. ? the program counter (pc) is loaded with the program reset address in the rom, 00000h. ? when the programmed oscillation stabilization time interval has elapsed, the instruction stored in rom location 00000h is fetched and executed. note to program the duration of the oscillation stabilization interval, make the appropriate settings to the watchdog timer control register, wdtcon, before entering stop mode.
reset and power-down s3 ck225/fk225 9- 2 notes
S3CK225/fk225 i/o p ort 10- 1 10 i/o ports port 0 port 0 control register(p0con) 20h, r/w, reset:00h .7 .6 .5 .4 .3 .2 .1 .0 msb lsb schmitt trigger input mode; pull-up; interrupt on falling edge schmitt trigger input mode; interrupt on rising edge schmitt trigger input mode; interrupt on rising or falling edge output mode, push-pull p0con bit-pair pin configuration settings: 0 0 0 1 1 0 1 1 p0.3/ int3 p0.2/ int2 p0.1/ int1 p0.0/ int0 figure 10-1. port 0 control register (p0con)
i/o port S3CK225/f k225 10- 2 port 1 port 1 control register (p1con) 21h, r/w, reset: 00h msb lsb p1.1/so p1.0/buz .7 .6 .5 .4 .3 .2 .1 .0 p1.3/si p1.2/sck input mode (sck, si) output mode, open-drain alternative function (buz, so, sck) output mode, push-pull p1con bit-pair pin configuration settings: 0 0 0 1 1 0 1 1 figure 10-2. port 1 control register (p1con) port 1 pull-up control register (p1pur) 22h,r/w, reset: 00h .7 .6 .5 .4 .3 .2 .1 .0 msb lsb disable pull-up resistor enable pull-up resistor p1 pull-up resistor settings: 0 1 p1.1 p1.0 p1.2 p1.3 not uesd figure 10-3. port 1 pull-up control register (p1pur)
S3CK225/fk225 i/o p ort 10- 3 port 2 port 2 high-byte control register (p2conh) 28h, r/w, reset: 00h msb lsb input mode input mode, pull-up open-drain output mode output mode, push-pull p2conh bit-pair pin configuration settings: 0 0 0 1 1 0 1 1 p2.7/seg7 p2.6/seg6 p2.5/seg5 p2.4/seg4 .7 .6 .5 .4 .3 .2 .1 .0 figure 10-4. port 2 high-byte control register (p2conh) port 2 low-byte control register (p2conl) 29h, r/w, reset: 00h msb lsb input mode input mode, pull-up open-drain output mode output mode, push-pull p2conl bit-pair pin configuration settings: 0 0 0 1 1 0 1 1 p2.3/seg3 p2.2/seg2 p2.1/seg1 p2.0/seg0 .7 .6 .5 .4 .3 .2 .1 .0 figure 10-5. port 2 low-byte control register (p2conl)
i/o port S3CK225/f k225 10- 4 port 3 port 3 high-byte control register (p3conh) 2ah, r/w, reset: 00h msb lsb input mode input mode, pull-up open-drain output mode output mode, push-pull p3conh bit-pair pin configuration settings: 0 0 0 1 1 0 1 1 p3.4/seg12 .7 .6 .5 .4 .3 .2 .1 .0 p3.7/seg15 p3.6/seg14 p3.5/seg13 figure 10-6. port 3 high-byte control register (p3conh) port 3 low-byte control register (p3conl) 2bh, r/w, reset: 00h msb lsb input mode input mode, pull-up open-drain output mode output mode, push-pull p3conl bit-pair pin configuration settings: 0 0 0 1 1 0 1 1 p3.3/seg11 p3.2/seg10 p3.1/seg9 p3.0/seg8 .7 .6 .5 .4 .3 .2 .1 .0 figure 10-7. port 3 low-byte control register (p3conl)
S3CK225/fk225 i/o p ort 10- 5 port 4 port 4 high-byte control register (p4conh) 30h, r/w, reset: 00h msb lsb input mode input mode, pull-up open-drain output mode output mode, push-pull p4conh bit-pair pin configuration settings: 0 0 0 1 1 0 1 1 p4.7/seg23 p4.6/seg22 p4.5/seg21 p4.4/seg20 .7 .6 .5 .4 .3 .2 .1 .0 figure 10-8. port 4 high-byte control register (p4conh) port 4 low-byte control register (p4conl) 31h, r/w, reset: 00h msb lsb input mode input mode, pull-up open-drain output mode output mode, push-pull p4conl bit-pair pin configuration settings: 0 0 0 1 1 0 1 1 p4.3/seg19 p4.2/seg18 p4.1/seg17 p4.0/seg16 .7 .6 .5 .4 .3 .2 .1 .0 figure 10-9. port 4 low-byte control register (p4conl)
i/o port S3CK225/f k225 10- 6 port 5 port 5 high-byte control register (p5conh) 32h, r/w, reset: 00h msb lsb input mode input mode, pull-up alternative function (ad7-ad4) output mode, push-pull p5conh bit-pair pin configuration settings: 0 0 0 1 1 0 1 1 p5.4/seg28/ ad4 .7 .6 .5 .4 .3 .2 .1 .0 p5.5/seg29/ ad5 p5.7/seg31/ ad7 p5.6/seg30/ ad6 figure 10-10. port 5 high-byte control register (p5conh) port 5 low-byte control register (p5conl) 33h, r/w, reset: 00h msb lsb input mode input mode, pull-up alternative function (ad3-ad0) output mode, push-pull p5conl bit-pair pin configuration settings: 0 0 0 1 1 0 1 1 p5.3/seg27/ ad3 p5.2/seg26/ ad2 p5.1/seg25/ ad1 p5.0/seg24/ ad0 .7 .6 .5 .4 .3 .2 .1 .0 figure 10-11. port 5 low-byte control register (p5conl)
S3CK225/fk225 i/o p ort 10- 7 port 6 port 6 control register (p6con) 34h, r/w, reset: 00h msb lsb input mode input mode, pull-up open-drain output mode output mode, push-pull p6con bit-pair pin configuration settings: 0 0 0 1 1 0 1 1 p6.0/com0 .7 .6 .5 .4 .3 .2 .1 .0 p6.3/com3 p6.2/com2 p6.1/com1 figure 10-12. port 6 control register (p6con) port 7 port 7 control register (p7con) 35h, r/w, reset: 00h msb lsb input mode (t0cap, t0clk, t2clk) input mode, pull-up (t0cap) alternative function (clkout, t3pwm, t0out/t0pwm, t2out/t2pwm) output mode, push-pull p7con bit-pair pin configuration settings: 0 0 0 1 1 0 1 1 p7.0/t2out/ t2pwm .7 .6 .5 .4 .3 .2 .1 .0 p7.3/t0cap/ clkout p7.2/t3pwm/ t0clk p7.1/t2clk/ t0out/t0pwm figure 10-13. port 7 control register (p7con)
i/o port S3CK225/f k225 10- 8 notes
S3CK225/fk225 basic timer/watchdog timer 11- 1 11 basic timer/watchdog timer overview wdtcon controls basic timer clock selection and watchdog timer clear bit. basic timer is used in two different ways : as a clock source to watchdog timer to provide an automatic reset mechanism in the event of a system malfunction (when watchdog function is enabled in rom code option) to signal the end of the required oscillation stabilization interval after a reset or stop mode release. the reset value of basic timer clock selection bits is decided by the rom code option. (see the section on rom code option for details). after reset, programmer can select the basic timer input clock using wdtcon. when watchdog function is enabled by the rom code option, programmer must set wdtcon.0 periodically within every 2048 basic timer input clock time to prevent system reset. msb lsb watchdog timer control register (wdtcon) 0dh, r/w, reset: x0h not used .7 .6 .5 .4 .3 .2 .1 .0 basic timer counter clock selection bits: 000 = fxx/2 001 = fxx/4 010 = fxx/16 011 = fxx/32 100 = fxx/128 101 = fxx/256 110 = fxx/1024 111 = fxx/2048 not used watchdog timer clear bit: 0 = don't care 1 = clear watchdog timer counter basic timer counter clear bit: 0 = don't care 1 = clear basic timer counter note: under the reset operation, basic timer input clock source is effected by rcod_opt.14-.12. after reset, it can be selected basic timer clock source by writing appropriate value to wdtcon.6-.4. figure 11-1. watchdog timer control register (wdtcon)
basic timer/watchdog timer S3CK225/fk2 25 11- 2 block diagram note: cpu start signal (bit 5 = 1/fb x 32) (power down release) clear reset 3-bit watchdog timer counter stop 8-bit basic timer counter (read only) mux mux reset wdtcon.6, .5, .4 data bus rcod_opt .14, .13, .12 reset or stop data bus clear bt int bt ovf bit 5 (note) rcod_opt.11 ovf (system reset) wdtcon.0 fb idle fxx/2 fxx/16 fxx/4 fxx/32 fxx/256 fxx/128 fxx/2048 fxx/1024 irq0.7 figure 11-2. basic timer & watchdog timer functional block diagram
S3CK225/fk225 wat ch timer 12- 1 12 watch timer overview the source of watch timer is fx/128 (main osc.) or fxt (sub osc.). the interval of watch timer interrupt can be selected by wtcon.3-2. table 12-1. watch timer control register (wtcon): 8-bit r/w bit name values function address wtcon.7 - .6 ? not used. 70h wtcon.5-.4 0 0 0.5 khz buzzer (buz) signal output 0 1 1 khz buzzer (buz) signal output 1 0 2 khz buzzer (buz) signal output 1 1 4 khz buzzer (buz) signal output wtcon.3 - .2 0 0 set watch timer interrupt to 1 sec. 0 1 set watch timer interrupt to 0.5 sec. 1 0 set watch timer interrupt to 0.25 sec. 1 1 set watch timer interrupt to 3.91 msec. wtcon.1 0 select fx/128 as the watch timer clock. 1 select fxt (sub osc) as the watch timer clock. wtcon.0 0 disable watch timer: clear frequency dividing circuits. 1 enable watch timer. notes : 1. the main clock frequency ( fx) is assumed to be 4.19 mhz. 2. the watch timer clock frequency ( fw) is assumed to be 32.768 khz.
watch timer s3ck22 5/fk225 12- 2 watch timer circuit diagram frequency dividing circuit fxt fx = main clock (4.19 mhz) fxt = sub clock (32.768 khz) fw = watch timer clock wtcon .4-.5 buzzer output overflow irq1.0 wtcon .1 wtcon .2-.3 fx/128 fw wtcon .0 clock selector selector circuit fw/2 6 (0.5 khz) mux fw/2 5 (1 khz) fw/2 4 (2 khz) fw/2 3 (4 khz) wt int fw/2 7 fw/2 13 fw/2 14 fw/2 15 (1 hz) f lcd = 512 hz fw/2 15 (1 hz) figure 12-1. watch timer circuit diagram
S3CK225/fk225 16-bi t timer 0 13- 1 13 16-bit timer 0 overview the 16-bit timer 0 is an 16-bit general-purpose timer/counter. timer 0 has three operating modes, one of which you select using the appropriate t0con setting: ? interval timer mode (toggle output at t0out pin) ? capture input mod e with a rising or falling edge trigger at the t0cap pin ? pwm mode (t0pwm) timer 0 has the following functional components: ? clock frequency divider ( fxx divided by 1024, 256, 64, 8 or 1) with multiplexer ? external clock input pin (t0clk) ? 16-bit counter (t0cnth/l), 16-bit comparator, and 16-bit reference data register (t0datah/l) ? i/o pins for capture input (t0cap), or pwm or match output (t0pwm, t0out) ? timer 0 overflow interrupt (irq0.1) and match/capture interrupt (irq0.0) generation ? timer 0 con trol register, t0con (40h, read/write)
16-bit timer 0 s3ck 225/fk225 13- 2 function description timer 0 interrupts (irq0.0, irq0.1) the timer 0 module can generate two interrupts, the timer 0 overflow interrupt (t0ovf), and the timer 0 match/capture interrupt (t0int). t0ovf is interrupt level irq0.1. t0int belongs to interrupt level irq0.0. interval timer function in interval timer mode, a match signal is generated and t0out is toggled when the counter value is identical to the value written to the t0 reference data register, t0datah/l. the match signal generates a timer 0 match interrupt (t0int) and clears the counter. if, for example, you write the value 0010h to t0datah/l and 04h to t0con, the counter will increment until it reaches 0010h. at this point, the t0 interrupt request is generated, the counter value is reset, and counting resumes. pulse width modulation mode pulse width modulation (pwm) mode lets you program the width (duration) of the pulse that is output at the t0pwm pin. as in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 data register. in pwm mode, however, the match signal does not clear the counter but can generate a match interrupt. the counter runs continuously, overflowing at ffffh, and then repeat the incrementing from 0000h. whenever an overflow is occurred, an overflow (ovf) interrupt can be generated. although you can use the match or the overflow interrupt in pwm mode, interrupts are not typically used in pwm-type applications. instead, the pulse at the t0pwm pin is held to low level as long as the reference data value is less than or equal to ( ) the counter value and then pulse is held to high level for as long as the data value is greater than (>) the counter value. one pulse width is equal to t clk capture mode in capture mode, a signal edge that is detected at the t0cap pin opens a gate and loads the current counter value into the t0 data register. you can select rising or falling edges to trigger this operation. timer 0 also gives you capture input source, the signal edge at the t0cap pin. you select the capture input by setting the value of the timer 0 capture input selection bit in the port 7 control register, p7con, (35h). when p7con.7-6 is 00, the t0cap input or normal input is selected .when p7con.7-6 is set to 11, normal output is selected. both kinds of timer 0 interrupts can be used in capture mode, the timer 0 overflow interrupt is generated whenever a counter overflow occurs, the timer 0 match/capture interrupt is generated whenever the counter value is loaded into the t0 data register. by reading the captured data value in t0datah/l, and assuming a specific value for the timer 0 clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the t0cap pin.
S3CK225/fk225 16-bi t timer 0 13- 3 timer 0 control register (t0con) you use the timer 0 control register, t0con, to ? select the timer 0 operating mode (interval timer, capture mode, or pwm mode) ? select the timer 0 input clock frequency ? clea r the timer 0 counter, t0cnth/l t0con is located at address 40h, and is read/written addressable. a reset clears t0con to ?00h?. this sets timer 0 to normal interval timer mode, and selects an input clock frequency of fxx/1024. to disable the counter operation, please set t0con.7-.5 to 111b. you can clear the timer 0 counter at any time during normal operation by writing a ?1? to t0con.2. timer 0 control register (t0con) 40h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer 0 counter clear bit: 0 = no effect 1 = clear the timer 0 counter (when write) timer 0 input clock selection bits: 000 = f x x/1024 010 = f x x/256 100 = f x x/64 110 = f x x/8 00 1 = f x x/1 011 = external clock (t0clk) falling edge 101 = external clock (t0clk) rising edge 111 = counter stop timer 0 operating mode selection bits: 00 = interval mode 01 = capture mode (capture on rising edge, counter running, ovf can occur) 10 = capture mode (capture on falling edge, counter running, ovf can occur) 11 = pwm mode (ovf & match interrupt can occur) not used figure 13-1. timer 0 control register (t0con)
16-bit timer 0 s3ck 225/fk225 13- 4 block diagram timer 0 data h/l register timer 0 buffer reg 16-bit comparator 16-bit up-counter (read only) counter clear signal or match clear match t0con.7-5 f xx /1024 f xx /8 f xx /256 f xx /64 f xx /1 t0ovf irq0.1 ovf t0con.2 t0int irq0.0 t0out t0pwm t0con.4-.3 r m u x v ss t0clk m u x m u x t0cap t0con.4-.3 data bus 8 data bus 8 figure 13-2. timer 0 functional block diagram
S3CK225/fk225 16-bi t timer 0 13- 5 timer 0 counter high-byte register (t0cnth) 43h, r, reset value: 00h msb lsb msb .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 lsb timer 0 counter low-byte register (t0cntl) 44h, r, reset value: 00h .7 .6 .5 .4 .3 .2 .1 .0 lsb timer 0 data high-byte register (t0datah) 41h, r/w, reset value: ffh msb .7 .6 .5 .4 .3 .2 .1 .0 lsb timer 0 data low-byte register (t0datal) 42h, r/w, reset value: ffh msb figure 13-3. timer 0 counter and data registers (t0cnth/l, t0datah/l)
16-bit timer 0 s3ck 225/fk225 13- 6 notes
S3CK225/fk225 16-bi t timer 1 14- 1 14 16-bit timer 1 overview the 16-bit timer 1 is an 16-bit general-purpose timer. timer 1 has the interval timer mode by using the appropriate t1con setting. timer 1 has the following functional components: ? clock frequency divider ( fxx divided by 256, 64, 8 or 1) with multiplexer ? t3of (from timer 3) is one of the clock frequencies. ? 16-bit counter (t1cnth/l), 16-bit comparator, and 16-bit reference data register (t1datah/l) ? timer 1 interrupt (irq0.2) generation ? timer 1 control register, t1con (48h, read/write) function description interval timer function the timer 1 module can generate an interrupt, the timer 1 match interrupt (t1int). t1int belongs to interrupt level irq0.2. in interval timer mode, a match signal is generated when the counter value is identical to the values written to the t1 reference data registers, t1datah/l. the match signal generates a timer 1 match interrupt (t1int) and clears the counter. if, for example, you write the value 0010h to t1datah/l and 0ch to t1con, the counter will increment until it reaches 10h. at this point, the t1 interrupt request is generated, the counter value is reset, and counting resumes.
16-bit timer 1 s3ck 225/fk225 14- 2 timer 1 control register (t1con) you use the timer 1 control register, t1con, to ? enable the timer 1 operating (int erval timer) ? select the timer 1 input clock frequency ? clear the timer 1 counter, t1cnt t1con is located, at address 48h, and is read/written addressable. a reset clears t1con to "00h". this sets timer 1 to disable interval timer mode, selects the t3of. you can clear the timer 1 counter at any time during normal operation by writing a ?1? to t1con.3 timer 1 control register 48h, r/w, reset; 00h .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer 1 count enable bit: 0 = disable counting operation 1 = enable counting operation timer 1 counter clear bit: 0 = no affect 1 = clear the timer 1 counter (when write) timer 1 input clock selection bits: 000 = t3of 010 = f x x/256 100 = fxx /64 110 = fxx /8 xx 1 = fxx not used note: for normal operation t1con.2 bit must be set 1. not used figure 14-1. timer 1 control register (t1con)
S3CK225/fk225 16-bi t timer 1 14- 3 block diagram timer 1 data h/l reg (read/write) timer 1 buffer reg 16-bit comparator 16-bit up-counter h/l (read only) match bit 3 counter clear (t1con.3) signal or match signal bits 7, 6, 5 m u x fxx/256 fxx/64 fxx/8 fxx/1 t3of bit 2 clear r data bus 8 data bus 8 note: t1con.3 bit is cleared automatically. irq0.2 da converter t1int figure 14-2. timer 1 functional block diagram
16-bit timer 1 s3ck 225/fk225 14- 4 timer 1 counter high-byte (t1cnth) 4bh, r, reset value: 00h .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer 1 counter low-byte (t1cntl) 4ch, r, reset value: 00h .7 .6 .5 .4 .3 .2 .1 .0 msb lsb figure 14-3. timer 1 counter register (t1cnth/l) timer 1 data high-byte register (t1datah) 49h, r/w, reset value: ffh .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer 1 data low-byte register (t1datal) 4ah, r/w, reset value: ffh .7 .6 .5 .4 .3 .2 .1 .0 msb lsb figure 14-4. timer 1 data register (t1datah/l)
S3CK225/fk225 8-bit timer 2 15- 1 15 8-bit timer 2 overview the 8-bit timer 2 is an 8-bit general-purpose timer/counter. timer 2 has two operating modes, one of which you select using the appropriate t2con setting: ? interval timer mode (toggle output at t2out pin) ? pwm mode (t2pwm) timer 2 has the following functional components: ? clock frequency divider (fxx divided by 1024, 256, or 64 ) with multiplexer ? external clock input pin (t2clk) ? 8-bit counter (t2cnt), 8-bit comparator, and 8-bit reference data register (t2data) ? i/o pin for pwm/match output (t2pwm, t2out) ? timer 2 overflow interrupt (irq0.4) and match interrupt (irq0.3) generation ? timer 2 control register, t2con (50h, read/write)
8-bit timer 2 s3ck2 25/fk225 15- 2 function description timer 2 interrupts (irq0.3 and irq0.4) the timer 2 module can generate two interrupts: the timer 2 overflow interrupt (t2ovf), and the timer 2 match interrupt (t2int). t2ovf is interrupt level irq0.4. t2int also belongs to interrupt level irq0.3. interval timer function in interval timer mode, a match signal is generated and t2out is toggled when the counter value is identical to the value written to the t2 reference data register, t2data. the match signal generates a timer 2 match interrupt (t2int) and clears the counter. if, for example, you write the value 10h to t2data and 0ch to t2con, the counter will increment until it reaches 10h. at this point, the t2 interrupt request is generated, the counter value is reset, and counting resumes. pulse width modulation mode pulse width modulation (pwm) mode lets you program the width (duration) of the pulse that is output at the t2pwm pin. as in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 2 data register. in pwm mode, however, the match signal does not clear the counter. instead, it runs continuously, overflowing at ffh, and then continues incrementing from 00h. although timer 2 overflow interrupt is occurred, this interrupt is not typically used in pwm-type applications. instead, the pulse at the t2pwm pin is held to low level as long as the reference data value is less than or equal to ( ) the counter value and then the pulse is held to high level for as long as the data value is greater than ( > ) the counter value. one pulse width is equal to t clk ? 256 .
S3CK225/fk225 8-bit timer 2 15- 3 timer 2 control register (t2con) you use the timer 2 control register, t2con, to ? select the timer 2 operating mode (interval mode, or pwm mode) ? select the timer 2 input clock frequency ? clear the timer 2 counter, t2cnt ? enable the timer 2 counting operation t2con is located in at address 50h, and is read/written addressable. a reset clears t2con to '00h'. this sets timer 2 to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables timer 2 counting operation. you can clear the timer 2 counter at any time during normal operation by writing a "1" to t2con.3 or the timer 2 counter is cleared by match signal. timer 2 control register 50h, r/w, reset: 00h .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer 2 count enable bit: 0 = disable counting operation 1 = enable counting operation timer 2 counter clear bit: 0 = no affect 1 = clear the timer 2 counter (when write) timer 2 input clock selection bits: 00 = f x x/1024 01 = f x x/256 10 = f x x/64 11 = external clock (t2clk) timer 2 operating mode selection bits: 0 = interval mode (t2out mode) 1 = pwm mode (ovf interrupt can occur) not used not used figure 15-1. timer 2 control register (t2con)
8-bit timer 2 s3ck2 25/fk225 15- 4 block diagram timer 2 data register (read/write) timer 2 buffer reg 8-bit comparator 8-bit up-counter (read only) clear match t2con.7-.6 f xx /1024 f xx /256 f xx /64 t2clk t2con.3 m u x t2ovf m u x t2out t2pwm t2con.5 data bus 8 data bus 8 irq0.3 irq0.4 bit 2 figure 15-2. timer 2 functional block diagram
S3CK225/fk225 8-bit timer 3 16- 1 16 8-bit timer 3 overview the S3CK225/fk225 micro-controller has an 8-bit counter called timer 3. timer 3, which can be used to generate the carrier frequency of a remote controller signal. timer 3 has two functions: ? as a normal interval timer, generating a timer 3 interrupt at programmed time intervals. ? to supply a clock source to the 16-bit timer/counter module, timer 1, for generating the timer 1 match interrupt.
8-bit timer 3 s3ck 225/fk225 16- 2 8-bit down counter timer 3 data high byte register mux t3con.0 (t3of) to other block (p7.2/t3pwm) irq0.5 (t3int) int.gen repeat control interrupt control m u x f xx /1 f xx /2 f xx /4 f xx /8 t3con.6-.7 t3con.2 timer 3 data low byte register clk t3con.4-.5 data bus 8 note: the value of the t3datal register is loaded into the 8-bit counter when the operation of the timer 3 starts. if a borrow occurs in the counter, the value of the t3datah register is loaded into the 8-bit counter. however, if the next borrow occurs, the value of the t3datal register is loaded into the 8-bit counter. figure 16-1. timer 3 functional block diagram
S3CK225/fk225 8-bit timer 3 16- 3 timer 3 control register (t3con) 54h, r/w, reset: 00h .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer 3 mode selection bit: 0 = one-shot mode 1 = repeating mode timer 3 output flip-flop control bit: 0 = t3of is low (t3pwm: low level for low data, high level for high data) 1 = t3of is high (t3pwm: high level for low data, low level for high data) timer 3 start/stop bit: 0 = stop timer 3 1 = start timer 3 not used timer 3 input clock selection bits: 00 = fxx 01 = fxx /2 10 = fxx /4 11 = fxx/8 timer 3 interrupt time selection bits: 00 = generating after low data is borrowed. 01 = generating after high data is borrowed. 10 = generating after low and high data is borrowed. 11 = invalid setting figure 16-2. timer 3 control register (t3con) timer 3 data high-byte register (t3datah) 55h, r/w, reset value: ffh .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer 3 data low-byte register (t3datal) 56h, r/w, reset value: ffh .7 .6 .5 .4 .3 .2 .1 .0 msb lsb figure 16-3. timer 3 data registers (t3datah/l)
8-bit timer 3 s3ck 225/fk225 16- 4 timer 3 pulse width calculations t low t high t low to generate the above repeated waveform consisted of low period time, t low , and high period time, t high . when t3of = 0, t low = (t3datal + 2) x 1/fxx, 0h < t3datal < 100h, where fxx = the selected clock. t high = (t3datah + 2) x 1/fxx, 0h < t3datah < 100h, where fxx = the selected clock. when t3of = 1, t low = (t3datah + 2) x 1/fxx, 0h < t3datah < 100h, where fxx = the selected clock. t high = (t3datal + 2) x 1/fxx, 0h < t3datal < 100h, where fxx = the selected clock. to make t low = 24 us and t high = 15 us. fx = 4 mhz, fxx = 4 mhz/4 = 1 mhz when t3of = 0, t low = 24 us = (t3datal + 2) /fx = (t3datal + 2) x 1us, t3datal = 22. t high = 15 us = (t3datah + 2) /fx = (t3datah + 2) x 1us, t3datah = 13. when t3of = 1, t high = 15 us = (t3datal + 2) /fx = (t3datal + 2) x 1us, t3datal = 13. t low = 24 us = (t3datah + 2) /fx = (t3datah + 2) x 1us, t3datah = 22.
S3CK225/fk225 8-bit timer 3 16- 5 timer 3 clock 0h t3of = '0' t3datal = 01-ffh t3datah = 00h t3of = '0' t3datal = 00h t3datah = 01-ffh t3of = '0' t3datal = 00h t3datah = 00h t3of = '1' t3datal = 00h t3datah = 00h low high low high timer 3 clock t3of = '1' t3datal = deh t3datah = 1eh t3of = '0' t3datal = deh t3datah = 1eh t3of = '1' t3datal = 7eh t3datah = 7eh t3of = '0' t3datal = 7eh t3datah = 7eh 0h 100h 200h e0h 20h 20h e0h 80h 80h 80h 80h figure 16-4. timer 3 output flip-flop waveforms in repeat mode
8-bit timer 3 s3ck 225/fk225 16- 6 f f programming tip ? to generate 38 khz, 1/3duty signal through p7.2 this example sets timer 3 to the repeat mode, sets the oscillation frequency as the timer 3 clock source, and t3datah and t3datal to make a 38 khz,1/3 duty carrier frequency. the program parameters are: 17.59 m s 37.9 khz 1/3 duty 8.795 m s ? timer 3 is used in repeat mode ? oscillation frequency is 4 mhz (0.25 m s) ? t3datah = 8.795 m s/0.25 m s = 35.18, t3datal = 17.59 m s/0.25 m s = 70.36 ? set p7.2 to t3pwm mode. start di ? ? ? ld r0,#(70-2) ld r1,#(35-2) ld r2,#000 00110b ld t3datal,r0 ; set 17.5 m s ld t3datah,r1 ; set 8.75 m s ld t3con,r2 ; clock source ? fxx ; select repeat mode for timer 3. ; start timer 3 operation. ; set timer 3 output flip-flop (t3of) low. ; bitr p7con.4 ; set p7.2 to t3pwm mode. bits p7con.5 ; this command generates 38 khz, 1/3 duty pulse signal through p7.2. ? ? ?
S3CK225/fk225 8-bit timer 3 16- 7 f f programming tip ? to generate a one pulse signal through p7.2 this example sets timer 3 to the one shot mode, sets the oscillation frequency as the timer 3 clock source, and t3datah and t3datal to make a 40 m s width pulse. the program parameters are: 40 m s ? timer 3 is used in one shot mode ? oscillation frequency is 4 mhz (1 clock = 0.25 m s) ? t3datah = 40 m s / 0.25 m s = 160, t3datal = 1 ? set p7.2 to t3pwm mode start di ? ? ? ld r0,#(160-2) ld r1,#1 ld r2,#00000001b ld t3datah,r0 ; set 40 m s ld t3datal,r1 ; set any value except 00h ld t3con,r2 ; clock source ? fxx ; select one shot mode for timer 3. ; stop timer 3 operation. ; set timer 3 output flip-flop (t3of) high bitr p7con.4 ; set p7.2 to t3pwm mode. bits p7con.5 ? ? pulse_out: ld r0,#00000101b ld t3con,r0 ; start timer 3 operation ; to make the pulse at this point. ? ; after the instruction is executed, 0.75 m s is required ? ; before the falling edge of the pulse starts. ?
8-bit timer 3 s3ck 225/fk225 16- 8 notes
S3CK225/fk225 seria l i/o interface 17- 1 17 serial i/o interfac e overview the sio module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. to ensure flexible data transmission rates, you can select an internal or external clock source. programming procedure to program the sio modules, follow these basic steps: 1. configure the i/o pins at port (so, sck, si) by loading the appropriate value to the p1con register, if necessary. 2. load an 8-bit value to the siocon register to properly configure the serial i/o module. in this operation, siocon.2 must be set to "1" to enable the data shifter. 3. when you transmit data to the serial buffer, write data to siodata and set siocon.3 to 1, t he shift operation starts.
serial i/o interface S3CK225/fk225 17- 2 sio control register (siocon) lsb msb serial i/o module control register (siocon) 58h, r/w, reset: 00h not used sio shift clock select bit: 0 = internal clock (p.s clock) 1 = external clock (sck) data direction control bit: 0 = msb-first 1 = lsb-first sio counter clear and shift start bit: 0 = no action 1 = clear 3-bit counter and start shifting sio shift operation enable bit: 0 = disable shifter and clock 1 = enable shfter and clock sio mode selction bit: 0 = rececive-only mode 1 = transmit/receive mode shift clock edge selction bit: 0 = tx at falling edge, rx at rising edge 1 = tx at rising edge, rx at falling edge .7 .6 .5 .4 .3 .2 .1 .0 figure 17-1. serial i/o module control registers (siocon) sio pre-scaler register (siops) the value stored in the sio pre- scaler registers, siops, lets you determine the sio clock rate (baud rate) as follows: baud rate = input clock( fxx/4)/(pre- scaler value + 1), or, sck input clock where fxx is a selected clock. lsb msb sio pre-scaler register (siops) 59h,r/w, reset: 00h baud rate = (fxx /4)/(siops + 1) .7 .6 .5 .4 .3 .2 .1 .0 figure 17-2. sio pre- scaler register (siops)
S3CK225/fk225 seria l i/o interface 17- 3 block diagram 3-bit counter mux 8-bit sio shift buffer (siodata) 8-bit p.s 1/2 fxx/2 siops sck siocon.7 (shift clock source select) clear clk clk si siocon.3 siocon.4 (edge select) siocon.5 (mode select) siocon.2 (shift enable) siocon.6 (lsb/msb first mode select) data bus 8 so irq0.6 (sio int) figure 17-3. sio function block diagram
serial i/o interface S3CK225/fk225 17- 4 serial i/o timing diagram so transmit complete irq0.6 set siocon.3 do7 do6 do5 do4 do3 do2 do1 do0 d17 d16 d15 d14 d13 d12 d11 d10 si sck figure 17-4. serial i/o timing in transmit/receive mode( tx at falling, siocon.4=0) irq0.6 do7 do6 do5 do4 do3 do2 do1 do0 d17 d16 d15 d14 d13 d12 d11 d10 sck transmit complete set siocon.3 si so figure 17-5. serial i/o timing in transmit/receive mode( tx at rising, siocon.4=1)
S3CK225/fk225 lcd c ontroller/driver 18- 1 18 lcd controller/driver overview the S3CK225/fk225 can directly drive an up-to 128-dots lcd panel. the lcd module has the following components: ? lcd controller/driver ? display ram (00h-0fh of page 2) for storing display data ? 32 segment output pins (seg0-seg31) ? 4 common output pins (com0-com3) bit settings in the lcd mode register, lmod, determine the lcd frame frequency, duty, and bias. the lcd control register lcon turns the lcd display on and off, and selects the segment pins used for display output. lcd data stored in the display ram locations are transferred to the segment signal pins automatically without program control. lcd controller/ driver 8 8-bit data bus 4 32 com0-com3 seg0-seg31 figure 18-1. lcd function diagram
lcd controller/driver S3CK225/fk225 18- 2 lcd circuit diagram com2 com0 com3 lmod lcon timing controller 02h.7 02h.6 02h.5 02h.4 00h.3 00h.2 00h.1 00h.0 0fh.4 0fh.5 0fh.6 0fh.7 mux mux mux 8 8 8 8 8 f lcd com control com1 seg31 seg30 seg29 seg28 seg0 seg8 seg7 seg6 seg5 seg4 segment driver 02h.3 02h.2 02h.1 02h.0 mux 8 lpot1,2 8 lcd voltage control figure 18-2. lcd circuit diagram
S3CK225/fk225 lcd c ontroller/driver 18- 3 lcd ram address area ram addresses 00h-0fh of page 2 are used as lcd data memory. when the bit value of a display segment is "1", the lcd display is turned on; when the bit value is "0", the display is turned off. display ram data are sent out through segment pins seg0-seg31 using a direct memory access (dma) method that is synchronized with the f lcd signal. ram addresses in this location that are not used for lcd display can be allocated to general-purpose use. 203h bit 7 bit 6 bit 5 bit 3 bit 2 bit 1 bit 0 bit 4 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 202h 201h 200h 207h 206h 205h 204h 20bh 20ah 209h 208h 20fh 20eh 20dh 20ch seg31 com3 com2 com1 com0 figure 18-3. lcd display data ram organization
lcd controller/driver S3CK225/fk225 18- 4 lcd control register (lcon, 60h) table 18-1. lcd control register (lcon) organization lcon bit setting description lcon.7 0 p4.7-p4.4 is selected 1 seg23-seg20 is selected, p4.7-p4.4 i/o is disabled lcon.6 0 p4.3-p4.0 is selected 1 seg19-seg16 is selected, p4.3-p4.0 i/o is disabled lcon.5 0 p3.7-p3.4 is selected 1 seg15-seg12 is selected, p3.7-p3.4 i/o is disabled lcon.4 0 p3.3-p3.0 is selected 1 seg11-seg8 is selected, p3.3-p3.0 i/o is disabled lcon.3 0 p2.7-p2.4 is selected 1 seg7-seg4 is selected, p2.7-p2.4 i/o is disabled lcon.2 0 p2.3-p2.0 is selected 1 seg3-seg0 is selected, p2.3-p2.0 i/o is disabled lcon.1 0 always logic zero lcon.0 0 lcd output low; turn display off 1 com and seg output is in display mode; turn display on table 18-2. relationship of lcon.0 and lmod.3 bit settings lcon.0 lmod.3 com0-com3 seg0-seg31 0 x output low; lcd display off output low; lcd display off 1 0 lcd display off signal output 1 com output corresponds to display mode seg output corresponds to display mode note: "x" means don't care.
S3CK225/fk225 lcd c ontroller/driver 18- 5 lcd mode register (lmod) the lcd mode control register lmod is mapped to ram addresses 61h. lmod controls these lcd functions: ? duty and bias selection (lmod.3 -lmod.0) ? lcdck clock frequency selection (lmod.5-lmod.4) the lcd clock signal, lcdck, determines the frequency of com signal scanning of each segment output. this is also referred to as the 'frame frequency'. reset clears the lmod and lcon register values to logic zero. this produces the following lcd control settings: ? display is turned off ? lcdck frequency is 64 hz the lcd display can continue to operate during idle and stop modes if a sub clock is running, sub clock is selected as watch timer clock, and watch timer is enabled. table 18-3. lcd clock signal (lcdck) frame frequency lcdck frequency (f lcd ) static 1/2 duty 1/3 duty 1/4 duty 64 hz 64 32 21 16 128 hz 128 64 43 32 256 hz 256 128 85 64 512 hz 512 256 171 128 note : because the clock source of lcdck is from watch timer module, watch timer must be enabled for lcd display.
lcd controller/driver S3CK225/fk225 18- 6 table 18-4. lcd mode control register (lmod) organization, 61h lmod.7 always logic zero. lmod.6 always logic zero. lmod.5 lmod.4 lcd clock (lcdck) frequency 0 0 f lcd = 64 hz (when fw is 32.768 khz) 0 1 f lcd = 128 hz (when fw is 32.768 khz) 1 0 f lcd = 256 hz (when fw is 32.768 khz) 1 1 f lcd = 512 hz (when fw is 32.768 khz) lmod.3 lmod.2 lmod.1 lmod.0 duty and bias selection for lcd display 0 x x x lcd display off signal output 1 0 0 0 1/4 duty, 1/3 bias 1 0 0 1 1/3 duty, 1/3 bias 1 0 1 1 1/3 duty, 1/2 bias 1 0 1 0 1/2 duty, 1/2 bias 1 1 x x static note: "x" means don't care. table 18-5. maximum number of display digits per duty cycle lcd duty lcd bias com output pins maximum seg display static static com0 32 1/2 1/2 com0-com1 32 2 1/3 1/2 com0-com2 32 3 1/3 1/3 com0-com2 32 3 1/4 1/3 com0-com3 32 4
S3CK225/fk225 lcd c ontroller/driver 18- 7 lcd port control registers (lpot1, lpot2) the lcd port control registers, lpot1 and lpot2, is used to control for selecting lcd signal or normal i/o pins. following a reset , the lpot1 and lpot2 values are cleared to "0". lsb msb lcd port control register1 (lpot1) 62h, r/w, reset: 00h seg31/p5.7 selection bit: 0 = normal i/o pin 1 = seg pin seg30/p5.6 selection bit: 0 = normal i/o pin 1 = seg pin seg27/p5.3 selection bit: 0 = normal i/o pin 1 = seg pin seg26/p5.2 selection bit: 0 = normal i/o pin 1 = seg pin seg29/p5.5 selection bit: 0 = normal i/o pin 1 = seg pin seg28/p5.4 selection bit: 0 = normal i/o pin 1 = seg pin .7 .6 .5 .4 .3 .2 .1 .0 seg25/p5.1 selection bit: 0 = normal i/o pin 1 = seg pin seg24/p5.0 selection bit: 0 = normal i/o pin 1 = seg pin figure 18-4. lcd port control resister1 (lpot1) lsb msb lcd port control register2 (lpot2) 63h, r/w, reset: 00h always logic zero com3/p6.3 selection bit: 0 = normal i/o pin 1 = com pin com2/p6.2 selection bit: 0 = normal i/o pin 1 = com pin .7 .6 .5 .4 .3 .2 .1 .0 com1/p6.1 selection bit: 0 = normal i/o pin 1 = com pin com0/p6.0 selection bit: 0 = normal i/o pin 1 = com pin figure 18-5. lcd port control resister2 (lpot2)
lcd controller/driver S3CK225/fk225 18- 8 lcd voltage dividing resistors static and 1/3 bias 1/2 bias v dd lcon.0 v lc1 v lc0 v lcd = v dd v ss r r r v dd lcon.0 v lc1 = v lc0 v lcd = v dd v ss r r r figure 18-6. internal voltage dividing resistor connection
S3CK225/fk225 lcd c ontroller/driver 18- 9 lcd com/seg signals the 32 lcd segment signal pins are connected to corresponding display ram locations at 00h-0fh of page 2. bits of the display ram are synchronized with the common signal output pins com0, com1, com2, and com3. when the bit value of a display ram location is "1", a select signal is sent to the corresponding segment pin. when the display bit is "0", a 'no-select' signal is sent to the corresponding segment pin. each bias has select and no-select signals. com-seg fr select non-select 1 frame com seg v dd v ss v dd v ss v dd v ss -v dd figure 18-7. select/no-select bias signals in static display mode
lcd controller/driver S3CK225/fk225 18- 10 fr select non-select 1 frame com v dd v lc1,0 v ss seg v ss com-seg v ss -v lc1,0 -v dd v dd v lc1,0 v dd v lc1,0 figure 18-8. select/no-select bias signals in 1/2 duty, 1/2 bias display mode -v dd v ss v dd v ss v dd v ss v dd com-seg com seg fr 1 frame non-select select figure 18-9. select/no-select bias signals in 1/3 duty, 1/3 bias display mode
S3CK225/fk225 lcd c ontroller/driver 18- 11 fr 1 frame com0 com1 seg0 seg1 com0 -seg0 com0 -seg1 com1 -seg0 com1 -seg1 0 1 0 1 note: v lc1 = v lc0 seg1 seg2 seg3 seg0 seg3.1 x c1 com0 com1 seg2.1 x c1 seg0.0 x c0 seg0.1 x c1 seg1.0 x c0 seg3.0 x c0 seg2.1 x c1 seg2.0 x c0 seg2.0 x c0 seg1.1 x c1 v dd v ss v lc1,0 v dd v ss v lc1,0 v dd v ss v lc1,0 v dd v ss v lc1,0 v dd -v dd v lc1,0 v ss -v lc1,0 v dd -v dd v lc1,0 v ss -v lc1,0 v dd -v dd v lc1,0 v ss -v lc1,0 v dd -v dd v lc1,0 v ss -v lc1,0 x x x x .0 .1 .2 .3 203h x x x x .0 .1 .2 .3 202h 0 1 1 0 .0 .1 .2 .3 201h 1 1 0 1 .0 .1 .2 .3 200h figure 18-10. lcd signal and wave forms example in 1/2 duty, 1/2 bias display mode
lcd controller/driver S3CK225/fk225 18- 12 com0 com1 seg0 seg1 com0 -seg0 com0 -seg1 com1 -seg0 com1 -seg1 com2 v lc2 v ss v lc1 v lc0 v dd v ss v lc1 v lc0 v dd v ss v lc1 v lc0 v dd v ss v lc1 v lc0 v dd v ss v lc1 v lc0 fr 1 frame 0 1 2 0 1 2 seg1.6 x c2 seg2.1 x c1 seg2.0 x c0 seg0.0 x c0 seg2.1 x c1 seg1.4 x c0 seg0.2 x c2 seg2.0 x c0 seg1.5 x c1 seg0.1 x c1 com1 seg0 seg1 seg2 com2 v dd -v lc1 v lc1 v lc0 v ss -v lc0 -v dd v dd -v lc1 v lc1 v lc0 v ss -v lc0 -v dd v dd -v lc1 v lc1 v lc0 v ss -v lc0 -v dd v dd -v lc1 v lc1 v lc0 v ss -v lc0 -v dd seg3 seg4 seg5 x x x x .0 .1 .2 .3 203h x x .4 .5 1 0 0 1 .0 .1 .2 .3 202h 0 0 .4 .5 1 0 1 0 .0 .1 .2 .3 201h 1 1 .4 .5 0 1 1 0 .0 .1 .2 .3 200h 1 1 .4 .5 com0 figure 18-11. lcd signals and wave forms example in 1/3 duty, 1/3 bias display mode
S3CK225/fk225 lcd c ontroller/driver 18- 13 1 frame 0 1 2 3 1 2 v dd v ss v lc1 v lc0 v dd v ss v lc1 v lc0 com0 com1 com3 seg0 com0 -seg0 com0 -seg1 com1 -seg1 com2 fr 0 3 v dd v ss v lc1 v lc0 v dd v ss v lc1 v lc0 v dd -v lc1 v lc1 v lc0 v ss -v lc0 -v dd v dd -v lc1 v lc1 v lc0 v ss -v lc0 -v dd v dd -v lc1 v lc1 v lc0 v ss -v lc0 -v dd v dd -v lc1 v lc1 v lc0 v ss -v lc0 -v dd v dd v ss v lc1 v lc0 v dd v ss v lc1 v lc0 seg1 com1 -seg0 seg1.7 x c3 seg2.1 x c1 seg1.4 x c0 seg0.0 x c0 seg0.1 x c1 seg1.5 x c1 seg0.3 x c3 seg2.0 x c0 seg1.6 x c2 seg0.2 x c2 com0 com1 com2 seg2 seg3 seg4 seg5 com3 seg0 seg1 x x x x .0 .1 .2 .3 203h x x .4 .5 1 0 0 1 .0 .1 .2 .3 202h 0 0 .4 .5 1 0 1 0 .0 .1 .2 .3 201h 1 1 .4 .5 0 1 1 0 .0 .1 .2 .3 200h 1 1 .4 .5 figure 18-12. lcd signals and wave forms example in 1/4 duty, 1/3 bias display mode
lcd controller/driver S3CK225/fk225 18- 14 notes
S3CK225/fk225 10-bi t a/d converter 19- 1 19 10-bit analog-to-digital converter overview the 10-bit a/d converter (adc) module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10 -bit digital values. the a nalog input level must lie between the av ref and av ss values. the a/d converter has the following components: ? analog comparator with successive approximation logic ? d/a converter logic (resistor string type) ? adc control register (adcon) ? eight multiplexed analog data input pins (ad0-ad7) ? 10-bit a/d conversion data output register (addatah/addatal) ? 8 -bit digital input port (alternately, i/o port) function description to initiate an analog-to-digital conversion procedure, at first you must set with alternative function for adc input enable at port 5, the pin set with alternative function can be used for adc analog input. and you write the channel selection data in the a/d converter control register adcon.4-.6 to select one of the eight analog input pins (ad0 ?ad7) and set the conversion start or enable bit, adcon.0. the read-write adcon register is located in address 5ch. the pins which are not used for adc can be used for normal i/o or seg signal. during a normal conversion, adc logic initially sets the successive approximation register to 800h (the approximate half-way point of an 10 -bit register). this register is then updated automatically during each conversion step. the successive approximation block performs 10-bit conversions for one input channel at a time. you can dynamically select different channels by manipulating the channel selection bit value (adcon.6? 4) in the adcon register. to start the a/d conversion, you should set the enable bit, adcon.0. when a conversion is completed, adcon.3, the end-of-conversion(eoc) bit is automatically set to 1 and the result is dumped into the addatah/addatal register where it can be read. the a/d converter then enters an idle state. remember to read the contents of addatah/addatal before another conversion starts. otherwise, the previous result will be overwritten by the next conversion result. note because the a/d converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog level at the ad0-ad7 input pins during a conversion procedure be kept to an absolute minimum. any change in the input level, perhaps due to noise, will invalidate the result. if the chip enters to stop or idle mode in conversion process, there will be a leakage current path in a/d block. you must use stop or idle mode after adc operation is finished.
10-bit a/d converter S3CK225/fk225 19- 2 conversion timing the a/d conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up a/d conversion. therefore, total of 50 clocks are required to complete an 10-bit conversion: when fxx/8 is selected for conversion clock with an 4.5 mhz fxx clock frequency, one clock cycle is 1.78 us. each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit 10-bit + set-up time = 50 clocks, 50 clock 1.78 us = 89 us at 0.56 mhz (4.5 mhz/8) note that a/d converter needs at least 25 m s for conversion time. a/d converter control register (adcon) the a/d converter control register, adcon, is located at address 5ch. it has three functions: ? analog input pin selection (bits 4?6) ? end-of-conversion status detection (bit 3) ? adc clock selection (bits 2 and 1) ? a/d operation start or disable (bit 0 ) after a reset, the start bit is turned off. you can select only one analog input channel at a time. other analog input pins (ad0-ad7) can be selected dynamically by manipulating the adcon.4?.6 bits. and the pins not used for analog input can be used for normal i/o or seg function. start or disable bit 0 = disable operation 1 = start operation (this bit is cleared automatically after end-of-conversion.) a/d converter control register (adcon) 5ch, r/w (eoc bit is read-only) .7 .6 .5 .4 .3 .2 .1 .0 msb lsb end-of-conversion bit 0 = not complete conversion 1 = complete conversion always logic zero a/d input pin selection bits: 000 = ad0 001 = ad1 010 = ad2 011 = ad3 100 = ad4 101 = ad5 110 = ad6 111 = ad7 clock selection bits: 00 = fxx/8 01 = fxx/4 10 = fxx/2 11 = fxx/1 figure 19-1. a/d converter control register (adcon)
S3CK225/fk225 10-bi t a/d converter 19- 3 conversion data register addatah/addatal 5dh/5eh, read only .9 .8 .7 .6 .5 .4 .3 .2 msb lsb (addatah) .1 .0 msb lsb (addatal) figure 19-2. a/d converter data register (addatah/addatal) internal reference voltage levels in the adc function block, the analog input voltage level is compared to the reference voltage. the analog input level must remain within the range av ss to av ref . different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. the reference voltage level for the first conversion bit is always 1/2 av ref . block diagram input pins ad0-ad7 (p5.0-p5.7) clock selector conversion result (addatah/addatal, 5dh/5eh) - + to adcon.3 (eoc flag) successive approximation logic & register av ref av ss analog comparator 10-bit d/a converter m u x adcon.4-.6 (select one input pin of the assigned pins) p5conh/l (assign pins to adc input) adcon.0 (ad/c enable) adcon.0 (ad/c enable) . . . adcon.2-.1 figure 19-3. a/d converter functional block diagram
10-bit a/d converter S3CK225/fk225 19- 4 av ss S3CK225 ad0-ad7 av ref reference voltage input (av ref v dd ) analog input pin v dd v dd 10 m f 103 101 + - c c r note: the symbol "r" signifies an offset resistor with a value of from 50 to 100 w . figure 19-4. recommended a/d converter circuit for highest absolute accuracy
S3CK225/fk225 d/a c onverter 20- 1 20 d/a converter overview the 10-bit d/a converter (dac) module uses successive approximation logic to convert 10-bit digital values to equivalent analog levels between v dd (1 - 1 1024 ) and v ss. this d/a converter consists of r?2r array structure. the d/a converter has the following components: ? r?2r array structure ? digital-to-analog converter control register (dacon) ? digital-to-analog converter data register (dadatah/dadatal) ? digital-to-analog converter output pin (dao) function description to initiate a digital-to-analog conversion procedure, you should set the digital-to-analog converter enable bit (dacon.0). the dacon register is located at the ram address 74h. you should write the digital value calculated to digital- to-analog converter data register (dadatah/dadatal). note if the chip enters to power-down mode, stop or idle, in conversion process, there will be current path in d/a converter block. so, it is necessary to cut off the current path before the instruction execution enters power-down mode.
d/a converter s3ck2 25/fk225 20- 2 data bus dacon.1 timer 1 match signal .0 .1 .2 .3 .4 .5 .6 .7 dadata .8 .0 .1 .2 .3 .4 .5 .6 .7 dac buffer .8 dao 2r 2r 2r 2r 2r 2r 2r 2r 2r 2r r r r r r r r r dacon.0 10-bit .9 .9 2r r figure 20- 1. dac circuit diagram enable/disable control bit: 0 = disable d/ac 1 = enable d/ac d/a converter control register (dacon) 74h, r/w, reset: 00h .7 .6 .5 .4 .3 .2 .1 .0 msb lsb data latch control bit: 0 = the value of dadata is always loaded into the dac buffer. 1 = the value of dadata is loaded into the dac buffer when the timer 1 match is occurred. not used figure 20-2. digital to analog converter control register (dacon)
S3CK225/fk225 d/a c onverter 20- 3 d/a converter data register (dadatah/dadatal) the dac data register, dadatah/dadatal is located at the ram address, 75h?76h. dadatah/dadatal specifies the digital data to generate analog voltage. a reset initializes the dadatah/dadatal value to "00h". the d/a converter output value, v dao , is calculated by the following formula. v dao = v dd n 1024 (n = 0-1023, dadatah/dadatal value) table 20-1. dadata setting to generate analog voltage dadatah.7 dadatah.6 dadatah.5 dadatah.4 dadatah.3 dadatah.2 dadatah.1 dadatah.0 dadatal.7 dadatal.6 v dao 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 v dd /2 1 0 1 0 0 0 0 0 0 0 0 v dd /2 2 0 0 1 0 0 0 0 0 0 0 v dd /2 3 0 0 0 1 0 0 0 0 0 0 v dd /2 4 0 0 0 0 1 0 0 0 0 0 v dd /2 5 0 0 0 0 0 1 0 0 0 0 v dd /2 6 0 0 0 0 0 0 1 0 0 0 v dd /2 7 0 0 0 0 0 0 0 1 0 0 v dd /2 8 0 0 0 0 0 0 0 0 1 0 v dd /2 9 0 0 0 0 0 0 0 0 0 1 v dd /2 10 note: these are the values determined by setting just one-bit of dadata.0-dadata.9. other values of dao can be obtained with superimposition.
d/a converter s3ck2 25/fk225 20- 4 conversion data register (dadatah/dadatal) 75h/76h, r/w .9 .8 .7 .6 .5 .4 .3 .2 msb lsb (dadatah) .1 - - - - - - msb lsb (dadatal) these bits should be always "0". .0 figure 20-3. d/a converter data register (dadatah/dadatal)
S3CK225/fk225 opera tional amplifier 21- 1 21 operational amplifier overview there are two op amps in the S3CK225/fk225. one is for filtering out the noise from input signals, the other is for amplifying input signals. these amplifiers can be used for another purpose. the amplifiers consists of the following components: ? fil amplifier (filin, filout) ? mic amplifier (micin, micout) ? op amp control register (opcon) ? vref generator op amp control register (opcon) mic amplifier control bit: 0 = disable mic amplifier 1 = enable mic amplifier op amp control register (opcon) 77h, r/w, reset: 00h .7 .6 .5 .4 .3 .2 .1 .0 msb lsb fil amplifier control bit: 0 = disable fil amplifier 1 = enable fil amplifier not used figure 21-1. op amp control register (opcon)
operational amplifier S3CK225/fk225 21- 2 vref generator - + - + opcon.0 opcon.1 filin filout vref micin micout 1 pf 300k 15k figure 21-2. op amp block diagram
S3CK225/fk225 elect rical data 22- 1 22 electrical data table 22-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ?0.3 to + 6.5 v input voltage v i ? ?0.3 to v dd + 0.3 v output voltage v o ? ?0.3 to v dd + 0.3 v output current high i oh one i/o pin active ?18 ma all i/o pins active ?60 output current low i ol one i/o pin active + 30 ma total pin current for port + 100 operating temperature t a ? ?25 to + 85 c storage temperature t stg ? ?65 to + 150 c table 22-2. d.c. electrical characteristics (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit operating voltage v dd fx = 8 mhz 3.0 ? 5.5 v fx = 4 mhz 2.4 ? 5.5 fx = 2 mhz 2.0 ? 5.5 input high voltage v ih1 all input pins except v ih2 0.8v dd ? v dd v v ih2 x in , xt in v dd ? 0.1 input low voltage v il1 all input pins except v il2 ? ? 0.2v dd v v il2 x in , xt in 0.1 output high voltage v oh v dd = 4.5 v to 5.5 v; i oh = ?1 ma, all output pins v dd ?1.0 ? ? v output low voltage v ol v dd = 4.5 v to 5.5 v; i ol = 10 ma, all output pins ? ? 2.0
electrical data s3 ck225/fk225 22- 2 table 22-2. d.c. electrical characteristics (continued) (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit input high leakage current i lih1 v in = v dd all input pins except i lih2 ? ? 3 ua i lih2 v in = v dd ; x in , xt in ? ? 20 input low leakage current i lil1 v in = 0 v all input pins except i lil2 ? ? ?3 i lil2 v in = 0 v; x in , xt in , reset ?20 output high leakage current i loh v out = v dd all i/o pins and output pins ? ? 3 output low leakage current i lol v out = 0 v all i/o pins and output pins ? ? ?3 oscillator feedback resistors r osc1 v dd = 5.0 v, t a = 25 c x in = vdd, x out = 0 v 400 750 1200 k w r osc2 v dd = 5.0 v, t a = 25 c xt in = vdd, xt out = 0 v 1500 3000 4500 pull-up resistor r l1 v in = 0 v; v dd = 5 v 10% port 0-7, t a = 25 c 25 50 100 r l2 v in = 0 v; v dd = 3 v 10% t a = 25 c, reset only 110 210 310 lcd voltage dividing resistor r lcd t a = 25 c 60 100 140 vlc1 output voltage v lc1 t a = 25 c v lcd = 2.5 v to 5.5 v 2/3v dd - 0.2v 2/3v dd 2/3v dd +0.2v v vlc0 output voltage v lc0 1/3 bias 1/3v dd - 0.2v 1/3v dd 1/3v dd +0.2v com output voltage deviation v dc v dd = v lc2 = 3v (vlcd-comi) i o = 15 m a, (i = 0-3) ? 60 120 mv seg output voltage deviation v ds v dd = v lc2 = 3v (vlcd-segi) i o = 15 m a, (i = 0-31) ? 60 120
S3CK225/fk225 elect rical data 22- 3 table 22-2. d.c. electrical characteristics (concluded) (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit supply current (1) i dd1 (2) v dd = 5 v 10% 8 mhz crystal oscillator ? 5.0 10 ma 2 mhz crystal oscillator 1.5 3 v dd = 3 v 10% 8 mhz crystal oscillator 3.0 6.0 2 mhz crystal oscillator 1.1 2.0 i dd2 idle mode: v dd = 5 v 10% 8 mhz crystal oscillator ? 1.0 2.0 ma 2 mhz crystal oscillator 0.5 1.0 idle mode: v dd = 3 v 10% 8 mhz crystal oscillator 0.5 1.0 2 mhz crystal oscillator 0.3 0.6 i dd3 sub operating mode: main-osc stop v dd = 3 v 10 % 32768 hz crystal oscillator ? 20 40 ua i dd4 sub-idle mode; main-osc stop v dd = 3 v 10 % 32768 hz crystal oscillator ? 6 15 i dd5 main stop mode; sub-osc stop. v dd = 5 v 10 %, t a = 25 c ? 1 3 v dd = 3 v 10 %, t a = 25 c 0.5 2 notes: 1, supply current does not include current drawn through internal pull-up resistors or external output current loads. 2. i dd1 and i dd2 includes a power consumption of sub oscillator. 3. i dd3 and i dd4 are the current when the main clock oscillation stop and the sub clock is used, and does not include lcd voltage dividing resistors. 4. i dd5 is the current when the main and sub clock oscillation stop.
electrical data s3 ck225/fk225 22- 4 table 22-3. a.c. electrical characteristics (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit interrupt input high, low width t inth , t intl p0.0?p0.3 v dd = 5 v ? 200 ? ns reset input low width t rsl v dd = 5 v 10 % 10 ? ? m s t inth t intl 0.8 v dd 0.2 v dd figure 22-1. input timing for external interrupts (port 0) reset t rsl 0.2 v dd figure 22-2. input timing for reset reset
S3CK225/fk225 elect rical data 22- 5 table 22-4. input/output capacitance (t a = ?25 c to + 85 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss . ? ? 10 pf output capacitance c out i/o capacitance c io table 22-5. data retention supply voltage in stop mode (t a = ?25 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 2 ? 5.5 v data retention supply current i dddr v dddr = 2 v ? ? 2 ua execution of stop instruction reset occur ~ ~ v dddr ~ ~ stop mode normal operating mode data retention mode t wait reset v dd note: t wait is decided by rcod_opt.14-.12 setting. when bit 14, 13, 12 of rcod_opt is "110"b, t wait is 1024 x 32 x 1/fxx. oscillation stabilization time 0.2v dd figure 22-3. stop mode release timing when initiated by a reset reset
electrical data s3 ck225/fk225 22- 6 execution of stop instruction v dddr ~ ~ data retention v dd normal operating mode ~ ~ stop mode osc start up time t wait oscillation stabilization time 0.2 v dd int note: t wait is decided by wdtcon register setting. when bit 6, 5, 4 of wdtcon is "110"b, t wait is 1024 x 32 x 1/fxx. figure 22-4. stop mode release timing initiated by interrupts
S3CK225/fk225 elect rical data 22- 7 table 22-6. a/d converter electrical characteristics (t a = ? 25 c to 85 c, v dd = 2.7 v to 5.5 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution ? 10 ? bit total accuracy v dd = 5.12 v ? ? 3 lsb integral linearity error ile av ref = 5.12 v ? 2 differential linearity error dle av ss = 0 v ? 2 offset error of top eot fxx = 8mhz 1 3 offset error of bottom eob f con = fxx/4 0.5 2 conversion time (1) t con 10-bit resolution 50 fxx/4, fxx = 8mhz 25 ? ? m s analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 ? ? m w analog reference voltage av ref ? 2.5 ? v dd v analog ground av ss ? v ss ? v ss +0.3 analog input current i adin av ref = v dd = 5 v ? ? 10 m a analog block current (2) i adc av ref = v dd = 5 v ? 1 3 ma av ref = v dd = 3 v 0.5 1.5 av ref = v dd = 5 v when power down mode 100 500 na notes: 1. 'conversion time' is the period between start and en d of conversion operation. 2. i adc is an operating current during a/d conversion. table 22-7. d/a converter electrical characteristics (t a = ? 25 c to 85 c, v dd = 2.7 v to 5.5 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution ? v dd = 5.12 v ? ? 10 bits absolute accuracy ? -3 ? 3 lsb differential linearity error dle -1 ? 1 lsb setup time t su ? ? 5 m s output resistance r o 20 30 40 k w
electrical data s3 ck225/fk225 22- 8 table 22-8. synchronous sio electrical characteristics (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v, v ss = 0 v, fxx = 8 mhz oscillator) parameter symbol conditions min typ max unit sck cycle time t cyc ? 250 ? ? ns serial clock high width t sckh ? 75 ? ? serial clock low width t sckl ? 75 ? ? serial output data delay time t od ? ? ? 65 serial input data setup time t id ? 50 ? ? serial input data hold time t ih ? 125 ? ? output data input data sck t sckh t cyc t sckl 0.8 v dd 0.2 v dd t od t id t ih 0.8 v dd 0.2 v dd si so figure 22-5. serial data transfer timing
S3CK225/fk225 elect rical data 22- 9 table 22-9. main oscillator frequency (f osc 1) (t a = ? 25 c to + 85 c v dd = 2.0 v to 5.5 v) oscillator clock circuit test condition min typ max unit crystal/ceramic x in c1 c2 x out v dd = 2.0 v ? 5.5 v 0.4 ? 2.0 mhz v dd = 2.4 v ? 5.5 v 4.0 v dd = 3.0 v ? 5.5 v 8.0 external clock x in x out v dd = 2.0 v ? 5.5 v 0.4 ? 2.0 mhz v dd = 2.4 v ? 5.5 v 4.0 v dd = 3.0 v ? 5.5 v 8.0 rc x in x out v dd = 5 v 0.4 ? 1 mhz v dd = 3 v 2 note: oscillation frequency and xin input frequency data are for oscillator characteristics only. table 22-10. main oscillator clock stabilization time (t st1 ) (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) oscillator test condition min typ max unit crystal v dd = 4.5 v to 5.5 v ? ? 10 ms v dd = 2.0 v to 5.5 v ? ? 30 ms ceramic v dd = 2.0 v to 5.5 v ? ? 4 ms external clock x in input high and low level width (t xh , t xl ) 62.5ns ? 125 m s ? note: oscillation stabilization time (t st1 ) is the time required for the cpu clock to return to its normal oscillation frequency after a power-on occurs, or when stop mode is ended by a reset signal.
electrical data s3 ck225/fk225 22- 10 x in t xh t xl 1/fosc1 v dd - 0.1 v 0.1 v figure 22-6. clock timing measurement at x in table 22-11. sub oscillator frequency (f osc2 ) (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) oscillator clock circuit test condition min typ max unit crystal xt in c1 c2 xt out ? 32 32.768 35 khz external clock xt in xt out ? 32 ? 100 khz note: oscillation frequency and xtin input frequency data are for oscillator characteristics only. xt in t xth t xtl 1/fosc2 v dd - 0.1 v 0.1 v figure 22-7. clock timing measurement at xt in
S3CK225/fk225 elect rical data 22- 11 table 22-12. sub oscillator (crystal) start up time (t st2 ) (t a = ? 25 c to + 85 c, v dd = 2.0 v to 5.5 v) oscillator test condition min typ max unit normal drive v dd = 4.5 v to 5.5 v ? 1 2 sec v dd = 2.0 v to 5.5 v ? ? 10 external clock xt in input high and low level width (t xth , t xtl ) 5 ? 15 m s note: oscillator stabilization time (t st2 ) is the time required for the oscillator to it's normal oscillation when stop mode is released by interrupts. table 22-13. op amplifier characteristics (v dd = 5 v, t a = 25 c) oscillator symbol test condition min typ max unit input voltage range vina fin = 1 khz ? 120 160 mvpp total harmonic distortion thd fin = 100 hz ? 10 khz ? ? 2 % input impedance rin micin input impedance 10 15 20 k w output inpedance rout micin output impedance ? 5 ? k w note: filin and filout are the same as micin and micout in characteristics at the same condition.
electrical data s3 ck225/fk225 22- 12 4 mhz 0.4 mhz 1 3 4 supply voltage (v) minimum instruction time = oscillator frequency 2 f cpu 8 mhz 2 mhz 5 6 7 2.4 5.5 figure 22-8. operating voltage range
S3CK225/fk225 mecha nical data 23- 1 23 mechanical data overview the S3CK225/fk225 is available in 64-qfp-1420f package. 64-qfp-1420f #64 20.00 ?0.20 23.90 ?0.30 14.00 ?0.20 17.90 ?0.30 #1 1.00 (1.00) 0.40 + 0.10 - 0.05 note : dimensions are in millimeters. 0.80 ?0.20 0.10 max 0.15 + 0.10 - 0.05 0-8 0.80 ?0.20 0.05 min 2.65 ?0.10 3.00 max 0.15 max figure 23-1. 64-pin qfp package dimensions (64-qfp-1420f)
mechanical data s3 ck225/fk225 23- 2 notes
S3CK225/fk225 s3fk2 25 flash mcu 24- 1 24 s3fk225 flash mcu overview the s3fk225 single-chip cmos microcontroller is the flash rom version of the S3CK225 microcontroller. it has an on-chip flash rom instead of masked rom. the flash rom is accessed by serial data formats. the s3fk225 is fully compatible with S3CK225, both in function and in electrical characteristics. because of its simple programming requirements, the s3fk225 is ideal for use as an evaluation for the S3CK225.
s3fk225 flash mcu s 3ck225/fk225 24- 2 com0/p6.0 com1/p6.1 com2/p6.2 com3/p6.3 p7.0/t2out/t2pwm p7.1/t2clk/t0out/t0pwm sdat /p7.2/t0clk/t3pwm sclk /p7.3/t0cap/clkout v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset reset /reset dao filin filout p2.0/seg0 p2.1/seg1 p2.2/seg2 p2.3/seg3 p2.4/seg4 p2.5/seg5 p2.6/seg6 p2.7/seg7 p3.0/seg8 p3.1/seg9 p3.2/seg10 p3.3/seg11 p3.4/seg12 vref micin micout p0.0/int0 p0.1/int1 p0.2/int2 p0.3/int3 p1.0/buz p1.1/so p1.2/sck p1.3/si avref avss p3.5/seg13 p3.6/seg14 p3.7/seg15 p4.0/seg16 p4.1/seg17 p4.2/seg18 p4.3/seg19 p4.4/seg20 p4.5/seg21 p4.6/seg22 p4.7/seg23 p5.0/seg24/ad0 p5.1/seg25/ad1 p5.2/seg26/ad2 p5.3/seg27/ad3 p5.4/seg28/ad4 p5.5/seg29/ad5 p5.6/seg30/ad6 p5.7/seg31/ad7 S3CK225/fk225 (64-qfp-1420f) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 figure 24-1. s3fk225 pin assignments (64-qfp-1420f)
S3CK225/fk225 s3fk2 25 flash mcu 24- 3 table 24-1. descriptions of pins used to read/write the flash rom during programming pin name pin no. i/o function sdat (p7.2) 7 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. sclk (p7.3) 8 i/o serial clock pin. input only pin. v pp (test) 13 i power supply pin for flash rom cell writing (indicates that flash enters into the writing mode). when 12.5 v is applied, flash is in writing mode and when 5 v is applied, flash is in reading mode. when flash is operating, hold gnd. reset (reset) 16 i chip initialization v dd /v ss (v dd /v ss ) 9/10 i logic power supply pin. v dd should be tied to +5 v during programming. note: maximum number of writing/erasing for s3fk225 is 100 times.
s3fk225 flash mcu s 3ck225/fk225 24- 4 notes
S3CK225/fk225 development tools 25- 1 25 development tools overview samsung provides a powerful and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with windows95/98/nt as its operating system can be used. one type of debugging tool including hardware and software is provided: the effective cost and powerful in-circuit emulator, invisiblemds, for calmrisc8. samsung also offers support software that includes debugger, compiler, assembler, and a program for setting options. calmshine: ide (integrated development environment) calmrisc8 samsung host interface for in-circuit emulator, calmshine, is a multi window based debugger for calmrisc8. calmshine provides pull-down, pop-up and tool-bar menus, mouse support, function/hot keys, syntax highlight, tool-tip, drag-and-drop and context-sensitive hyper-linked help. it has an advanced, multiple- windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added or removed, docked or undocked completely. invisible mds: in-circuit emulator the evaluation chip of calmrisc8 has a basic debugging utility block. using this block, evaluation chip directly interfaces with host through only communication wire. so, invisiblemds offers simple and powerful debugging environment. calmrisc8 c-compiler: calm8cc the calmrisc8 compiler offers the standard features of the c language, plus many extensions for mcu applications, such as interrupt handling in c and data placement controls, designed to take fully advantage of calmrisc8 facilities. it conforms to the ansi specification. it supports standard library of functions applicable to mcu systems. the standard library also conforms to the ansi standard. it generates highly size-optimized code for calmrisc8 by fully utilizing calmrisc8 architecture. it is available in a windows version integrated with the calmshine. calmrisc8 relocatable assembler: calm8asm the calmrisc8 assembler is a relocatable assembler for samsung's calmrisc8 mcu and its mac816 and mac2424 coprocessors. it translates a source file containing assembly language statements into a relocatable machine object code file in samsung format. it runs on windows95 compatible operating systems. it supports macros and conditional assembly. it produces the relocatable object code only, so the user should link object files. object files can be linked with other object files and loaded into memory. calmrisc8 linker: calm8link the calmrisc8 linker combines samsung object format files and library files and generates absolute, machine- code executable hex programs or binary files for calmrisc8 mcu and its mac816 and mac2424 coprocessors. it generates the map file, which shows the physical addresses to which each section and symbol is bounded, start addresses of each section and symbol, and size of them. it runs on windows95 compatible operating
development tools S3CK225/fk225 25- 2 systems. emulation probe board configuration s3ek220x jp4 tavss avss vss tavref avref vdd reset u8 10 20 30 9 19 29 10 20 30 9 19 29 u5 power on power select power vdd off user vdd u14 s1 dc5v 500ma jp5 e-5v 78r33 10 20 30 9 19 29 1 9 31 19 29 10 32 20 30 jp1 33 39 63 49 59 40 64 50 60 jp2 vdd vss k6a1016c-jciz con1 evmat0 evmat3 ext_bk0 ext_bk3 xtal oscclk u1 clk_select jp3 c2 c1 y1 d3 run d2 power 74hc08 u11 ep-k225 12/16/2002 rev 0 u10 u7 bkreqx jtag con2 sm1409a u12 30 20 10 40 u19 vdd e-3v 34 2 figure 25-1. emulation probe board configuration invisible mds connector = 10-pin/normal pitch (2.54mm) = jtag pin no. pin name pin no. pin name 1 v dd 6 ptd0_txd 2 pntrst_ninit 7 gnd 3 ptck_mclk 8 uclk 4 ptms 9 jtagsel 5 ptdi_rxd 10 ?
S3CK225/fk225 development tools 25- 3 external event input headers these input headers are used to add the break condition to the core status externally when the break using calmbreaker occurs in the evaluation chip. ext_bk ext_bk0 ext_bk1 ext_bk2 ext_bk3 evachip_extbk[0] evachip_extbk[1] evachip_extbk[2] evachip_extbk[3] event match output headers four event match signals and one combination event signal are occurred by the calmbreaker in the evaluation chip. these signals are transmitted through the evaluation chip. evmat evmat0 evmat1 evmat2 evmat3 evachip_extbk[0] evachip_extbk[1] evachip_extbk[2] evachip_extbk[3] external break input headers (u7) this input pin is used to break during the evaluation chip run. evachip_bkreqx bkreqx
development tools S3CK225/fk225 25- 4 power selection u12 state description vdd power _vdd off user _vdd power select same power source from target system target system mds v ss dc jack power user power cpu ep-k225 v ss vdd power _vdd off user _vdd power select same power source from dc jack dc jack power user power target system mds v ss cpu ep-k225 v ss clock selection u1 state description xtali osc clksel x-tal xtalo off mxin mxout oscclk osc[y1] is used to clock source for evaluation chip cpu ep-k225 osc clk xmin mxout xtali osc clksel x-tal xtalo off mxin mxout oscclk x-tal[jp3] is used to clock source for evaluation chip cpu ep-k225 xmin mxout jp3 xtalo xtali
S3CK225/fk225 development tools 25- 5 vref selection jp4 state description tavref uavref tavss uavss avref avss same avref of eva chip from tavref of target system. tavref uavref tavss uavss avref avss same avref of eva chip from tavref of target system. use clock setting for external clock mode proper crystal and capacitors for main clock should be inserted into pin socket on the ie board as follows; c y2 x-tal c x in x out sub clock setting for sub-clock mode a crystal, 32.768 khz and capacitors should be inserted into pin socket on the ie board as follows; c y1 x-tal c xt in xt out r note: the value of resistor is 0 k w.
development tools S3CK225/fk225 25- 6 jp1, jp2 pin assignment jp1, 2 are the signals of ie-k225 and their pin assignment is the same as the pin of S3CK225. jp1 function jp1 function jp2 function jp2 function 1 p6.0 2 p6.1 33 p5.7 34 p5.6 3 p6.2 4 p6.3 36 p5.5 36 p5.4 5 p7.0 6 p7.1 37 p5.3 38 p5.2 7 p7.2 8 p7.3 39 p5.1 40 p5.0 9 vdd 10 vss 41 p4.7 42 p4.6 11 xout[nc] 12 xin[nc] 43 p4.5 44 p4.4 13 test 14 xtin[nc] 45 p4.3 46 p4.2 15 xtout[nc] 16 reset 47 p4.1 48 p4.0 17 dao 18 filin 49 p3.7 50 p3.6 19 filout 20 vref 51 p3.5 52 p3.4 21 micin 22 micout 53 p3.3 54 p3.2 23 p0.0 24 p0.1 55 p3.1 56 p3.0 25 p0.2 26 p0.3 57 p2.7 58 p2.6 27 p1.0 28 p1.1 59 p2.5 60 p2.4 29 p1.2 30 p1.3 61 p2.3 62 p2.2 31 tavref 32 tavss 63 p2.1 64 p2.0

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